TH29875B - Multiple division frequency division - Google Patents

Abstract

The DC60 (18/03/42) multiple frequency divider includes a chain of series-connected frequency divider units, each of which responds to the first state of the incoming control signal by applying A reference clock signal to generate an output signal with a frequency equal to the divided clock frequency. with the first divisor and each unit responds to the second state of the control signal by using This reference clock signal is used to generate an output signal with a frequency equal to the reference clock frequency. Based on the second divisor, this output signal is supplied to the subsequent frequency divider unit as sequence in this chain Dividing by this first and second divisor causes this frequency divider to change. sequentially through the first and second predetermined state sequences Each frequency divider also answers Respond further to the third state of the control signal by initially designating this frequency divider as An initial state, which is shared with both the first and second predefined status sequences. In this way, the frequency divider in this initial state responds immediately to subsequent incomings. of the first state of the control signal and will respond promptly to subsequent incoming supply within the latter of the second state of the control signal The incoming of the opening control signal through the swall. An incoming low with a pre-defined value closes the division by this second divisor. frequency divider Each continues to generate an output control signal with a predefined value whenever This frequency divider is in this initial state. A multiple divider frequency divider includes a chain of series connected frequency dividers. Each unit responds to the first state of the incoming control signal by using a reference clock signal to generate an output signal with a frequency equal to the clock frequency divided by the first divisor. and each unit responds to the second state of the control signal by using this reference clock signal to generate the available output signal. The frequency which is equal to the reference clock frequency divided by the second divisor, this output signal is supplied to the respective frequency divider units in this chain. Dividing by this first and second divisor causes this frequency divider to change sequentially through the first and second predefined sequences. Each frequency divider also responds to the third state of the control signal by initializing this frequency divider as an initial state which is shared with both the first predefined and Second, with this, the frequency divider in this initial state responds immediately to the subsequent incoming of the first state of the control signal and immediately responds to the subsequent incoming of the state. the second of the control signal The incoming swing opening control signal with a predefined value is closed through this second divider. Each frequency divider continues to generate an output control signal. another which has a predefined value whenever this frequency divider is in this initial state.

Claims (2)

1. Frequency divisor which has the ability to selectively divide by one and two more than one divisor. Where this frequency divider consists of: trajectory for receiving a reference clock signal with a reference clock frequency; A path for receiving a number of control signals. A method that responds to the first state of the control signal for using a reference clock signal to generate a frequency output. Which is equal to the reference clock frequency divided by the denominator one, herein by this divisor one causes this frequency divider to change through the order of the state Predetermined first order; A second path that responds to the second state of the control signal for using this reference clock signal. To generate an output signal with a frequency which is equal to the reference clock frequency divided by this second divisor, herein by the second divisor causes this frequency divider to change through a pre-defined state sequence. two; And a third path, which responds to the third state of the control signal for the initial designation of this frequency divider to the initial state, which is shared with both the first and second predefined state sequences. Which by this The frequency divider in the preliminary state responds immediately to the payout. Subsequent to the first state of the control signal and will respond promptly to the subsequent inlet of the first state of the control signal and will respond immediately to the subsequent inlet of The second state of these control signals 2. The frequency divisor of the clause. 1 in which here This first and second way The excitation will be suppressed as long as the third state of the control signal is further acknowledged by this receiving device. 3. The frequency divisor of claim 1, which also continues: The path for receiving the opening control signal of the swallow; The method for disabling this second device whenever the slave-wall launch control signal is not set to a predetermined value; And the path for generating a pre-defined output control signal whenever this frequency divider is in its preliminary state. 4. Frequency divisor of claim 1, in which the first divisor is Equal to two And the second divisor is equal to three. 5. The multiple frequency divisor Which includes: One number of series-connected frequency divider units Each of which includes A means for obtaining a reference clock signal with a reference clock frequency; A path for receiving a number of control signals. A method that responds to the first state of the control signal for using a reference clock signal to generate the output. A input with a frequency equal to the reference clock frequency divided by the first divisor, herein by this divisor one causes this frequency divider to change through the first predetermined sequence of states; A second path, which responds to the second state of the control signal, for using this reference clock to generate an output signal with a frequency equal to the reference clock frequency divided by this second divisor, herein, division by the numerator. The second divisor causes this frequency divider to change through the second pre-defined state sequence; And a third path, which responds to the third state of the control signal for the initial designation of this frequency divider to the original state, which is shared with both the pre-defined state sequence. First and second order Which by this The frequency divider in the preliminary state responds immediately to the subsequent inlet of the first state of the control signal and responds immediately to the subsequent inlet of that state. Two of these control signals The path for receiving the opening control signal of the swallow; Path for closing this second route whenever the sidewall opening control signal is not set to a predetermined value; And a path for generating a pre-defined output control signal whenever this frequency divider is in its preliminary state, wherein the class i frequency divider in multiple frequency divisors where Serialized, the ith output signal is supplied to the tiered frequency divider (i + I) for use as a reference clock signal in the tiered frequency divider (i + I) and the rated frequency divider. Class i supplies the ith output control signal to the tiered frequency divider (i + I) for use as a control signal, open the sidewall in the tiered frequency divider (iI). The multiplicative frequency divider of claim 5, which is further included, is one or more series-connected second frequency divider units for supplying the input reference clock to the frequency divider unit at These multiple units are serially connected, where each second frequency divider unit does not have a third device for the initial designation of this frequency divider as its initial state. Many times of claim 5, herein Divide each of these frequencies to this first and second device. The excitation will be suppressed as long as the third state of the control signal is further acknowledged by this receiving device. 8. Multiple division frequency divider of claim 5, herein The first divisor is equal to two. And the second denominator is equal to three 9. Methods of controlling the frequency divider to perform a selective operation of the frequency division by the first and second divisors greater than one. This method consists of steps of: obtaining a reference clock signal with a reference clock frequency; Reception of a certain number of control signals; Response to the first state of the control signal by using a reference clock signal to generate an output signal with a frequency equal to the reference clock frequency divided by the denominator one, in which the division by the first denominator includes a step. Of the transition through the first predefined status sequence; A response to the second state of a control signal by using a reference clock signal to generate an output signal with a frequency that is equal to the reference clock frequency divided by the second divisor. Division by the second divisor includes transitions of the second predetermined sequence of states; And the response to the third state of the control contract by initially assigning this frequency divider to the initial state, which is shared with both the first and second predefined positions. Which by this The frequency divider in the preliminary state responds immediately to the subsequent inlet of the first state of the control signal and reacts immediately to the subsequent inlet of the second state of the control signal. 1 0. Clause 9 Method of Clause, wherein the procedures of responding to the first and second states of the control signal shall not be performed as long as The third state of this control signal is further received by this receiving device 1. 1. Method of claim No. 9, which also includes the procedure of: receiving a signal, controlling the opening of the swallow; Prohibition of the phase of response to the second state of the control signal whenever the opening control signal is not received. Adjustment to a predefined value; And generating a pre-defined output control signal as long as the frequency divider is in this initial state 1 2. Method of claim Clause 9 in which the first divisor equals two. And the second divisor is going to be three.