TH21911EX - "Arrangement of circuits for synchronization" - Google Patents

Abstract

The invention involves organizing a synchronization instrument integrated into the unit. Multiplexing / D multiplexing (1) which receives the bit stream associated with the dataset. The different values and positions of the bits within a given part of the sequential bit sequence of each dataset. Therefore, a given check calculation gives a given value (for example, "O"). The sequence of tiled bits received with the specified part of the sequence. Of tiled bits And belong to the received data set respectively It is computed in order to establish a network where the check calculations will give the specified values. When a manipulation is discovered, it is assumed that the boundary between two adjacent datasets is established through a sequence of bits of Determined part of the tiled sequence of bits Each incoming bit stream will be synchronized. Through the medium or the medium of the control diagram or the control logic (4, 9) by the time delay. Received with synchronization as a series-parallel converter (3) for the respective bit currents. The synchronized parallel-formatted bit stream (25) is passed through the control schematic. Or logic to control (4) to memory (5) which will send bit stream to the Pass-through connections (8) through buffer circuits (6) and parallel-series converters (7).

Claims (1)

1.Synchronization circuit arrangement included in multiplexing / decomposition units Which serves to divide the bit stream in order To be the specified data set Clearly sorted in order This is to provide the boundaries between the data sets that are aligned. Can be established By making constant selection Which the values and positions of the bits within the section Given the sequence of tiled bits in each data set sent, the required check calculation will give the specified value. (For example, "O") where the numbered bit sequence