CN102355407B - Configurable bit replacement computation system and method - Google Patents
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Abstract
The invention discloses a configurable bit replacement computation system and a method. The system comprises a routing selection algorithm unit, a configuration information storage and a bit replacement computation unit which are connected in turn, wherein the routing selection algorithm unit is used for generating corresponding configuration information according to a preset network configuration principle and then sending the configuration information to the configuration information storage; the configuration information storage is used for receiving and storing the configuration information sent by the routing selection algorithm unit and sending the configuration information to the bit replacement computation unit; the bit replacement computation unit is used for receiving the configuration information sent by the configuration information storage and configuring a corresponding network; and after finishing configuration, the configured bit replacement computation unit is used for processing according to a replacement input data and generating a replacement output result. The configurable bit replacement computation system and the method provided by the invention have the advantages of simple structure, small realizing area of circuit, easy expandability, configurability and simple configurability algorithm.
Description
Technical field
The present invention relates to information security technology and field of computer technology, particularly, relate to a kind of configurable bit replacement computation system and method.
Background technology
Along with informationization, digitlization and the networking day by day of modern society, people are more and more extensive to the demand of information security technology.The application of information security technology, from traditional military affairs, political department, progressively expands to each corner of social and economic activities; Safety information product becomes the important leverage of the optimum running of entire society, and the safety of protection information has also become the important topic of science and technology field.
In information security system, cryptographic algorithm is basis and the core technology of information security, and bit permutation is significant in cryptographic algorithm.The functions such as confusion diffusion that bit permutation provides byte manipulation to realize.Displacement, as the primary means of diffusion, is widely applied in cryptographic algorithm.In addition,, in Computer Architecture, along with the development of multimedia and information security technology, fast bit displacement also will become an important development direction of the processor of byte-oriented.
The permutation network adopting now has GRP, OMFLIP, BFLY, IBFLY and BENES etc.GRP network log
2n level N selects 1 data selector, and every one-level all needs N position configuration bit, because whole network launches a plurality of permute units, adopts MUX, so complex structure, it is very large that circuit is realized area, and placement algorithm is complicated, and autgmentability is poor; OMFLIP network connects a Flip network by an Omega network and forms.The Omega network of N position input is by identical log
2n layer forms, and every one deck has N individual 2 to select 1 data selector, and the Flip network of N position input is the retrodirective mirror picture of the Omega network of N position input, also by identical log
2n layer forms, so Omega-flip network has 2log
2n layer, it is large that circuit is realized area, and placement algorithm is complicated.BFLY network and IBFLY network, the BFLY network of N position input is the retrodirective mirror picture of the IBFLY network of N position input, all uses log
2n level network is realized displacement, and every one-level has N individual 2 to select 1 data selector, and BFLY network and IBFLY network configuration are simple, can expand, and easily configuration, but in the process of displacement, can block generation mistake.BENES network is that a BFLY and IBFLY network are in series, and merges into 1 grade for middle adjacent 2 grades, so a total 2log
2n-1 level, every one-level has N individual 2 to select 1 data selector, and BENES network has advantages of BFLY network and IBFLY network, and can not produce choking phenomenon, but exists circuit to realize the problem that area is larger.
In sum, in realizing process of the present invention, inventor finds at least to exist in prior art complex structure, circuit to realize that area is large, placement algorithm is complicated, autgmentability is poor with replacement process, the defects such as obstruction easily occurs.
Summary of the invention
The object of the invention is to, for the problems referred to above, propose a kind of configurable bit replacement computation system,, circuit simple with implementation structure realized little, the easy expansion of area, the configurable and simple advantage of placement algorithm.
For achieving the above object, the technical solution used in the present invention is: a kind of configurable bit replacement computation system, comprise the routing algorithm unit, configuration information memory and the bit permutation arithmetic element that connect successively, wherein:
Described routing algorithm unit, for according to default network configuration principle, generates after corresponding configuration information, and described configuration information is sent to configuration information memory; Default network configuration principle, is specifically as follows: in every one-level network configuration, respectively input and output bit is divided into groups, the bit of mutual exclusion bit centering is not on the same group.
Described configuration information memory, the configuration information sending for receiving described routing algorithm unit, stores, and described configuration information is sent to bit permutation arithmetic element;
Described bit permutation arithmetic element, the configuration information sending for receiving described configuration information memory, is configured corresponding network; After having configured, the bit permutation arithmetic element having configured, processes according to displacement input data, generates displacement Output rusults.
Further, described bit permutation arithmetic element, comprising can arbitrary extension and the multistage basic bit in-place computation subelement that arranges of upper and lower Symmetric Composite, the cascade network that is arranged between adjacent two-stage basic bit in-place computation subelement and can cross exchanged, and the classification recurrence mutual exclusion dispensing unit for transmitting control signal to multistage basic bit in-place computation subelement according to rank; Described cascade network that can cross exchanged, up-down structure full symmetric.
Further, every grade of basic bit in-place computation subelement, the switching network being equipped with about comprising and the arbitrarily permutation network of bit wide; Every grade of basic bit in-place computation subelement, according to permutation and combination rule, completes the displacement of N bit data, needs to carry out
operation; Wherein, described switching network is carried out
operation, permutation network is carried out
operation.
Further, described permutation network, comprises the multistage bit permutation sub-network that the identical and upper and lower symmetrical cascade of structure arranges; The upper and lower symmetric arrays of described multistage bit permutation sub-network, the major network of composition place permutation network;
At the front end of described major network, be provided with preposition switching network; In the rear end of major network, be provided with rearmounted switching network; Described preposition switching network, major network and rearmounted switching network, connect by laterally zygomorphic intersection level on line successively, forms entire cascaded network.
Further, every grade of basic bit in-place computation subelement is 4 * 4 bit permutation operator unit; Described 4 * 4 bit permutation operator unit comprise first to fourth input bit I
1, I
2, I
3with I
4, the first to ten network node, first to 10 select 1 data selector Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux8, Mux9 and Mux10, the first to five configuration bit C
1, C
2, C
3, C
4with C
5, and first to fourth output bit O
1, O
2, O
3with O
4; Wherein:
Described the first input bit I
1, select the first input end and the 52 of 1 data selector Mux3 to select the first input end of 1 data selector Mux5 to be connected with the 32 respectively; The second input bit I
2, select the first input end and the 22 of 1 data selector Mux1 to select the first input end of 1 data selector Mux2 to be connected with the 1 respectively; The 3rd input bit I
3, select the second input and the 22 of 1 data selector Mux1 to select the second input of 1 data selector Mux2 to be connected with the 1 respectively; The 4th input bit I
4, select the second input and the 62 of 1 data selector Mux4 to select the second input of 1 data selector Mux6 to be connected with the 42 respectively;
The described the 1 selects the output of 1 data selector Mux1, selects the second input and the 52 of 1 data selector Mux3 to select the second input of 1 data selector Mux5 to be connected respectively with the 32; The 22 selects the output of 1 data selector Mux2, selects the first input end and the 62 of 1 data selector Mux4 to select the first input end of 1 data selector Mux6 to be connected respectively with the 42;
The described the 32 selects the output of 1 data selector Mux3, selects the first input end and the 82 of 1 data selector Mux7 to select the first input end of 1 data selector Mux8 to be connected respectively with the 72; The 42 selects the output of 1 data selector Mux4, selects the second input and the 82 of 1 data selector Mux7 to select the second input of 1 data selector Mux8 to be connected respectively with the 72; The 52 selects the output of 1 data selector Mux5, selects the first input end and the 10 of 1 data selector Mux9 to select the first input end of 1 data selector Mux10 to be connected respectively with the 92; The 62 selects the output of 1 data selector Mux6, selects the second input and the 10 of 1 data selector Mux9 to select the second input of 1 data selector Mux10 to be connected respectively with the 92;
The described the 72 selects the output of 1 data selector Mux7, exports the first output bit O
1; The 82 selects the output of 1 data selector Mux8, exports the second output bit O
2; The 92 selects the output of 1 data selector Mux9, exports the 3rd output bit O
3; The 10 selects the output of 1 data selector Mux10, exports the 4th output bit O
4;
Described the first configuration bit C1 selects 1 data selector Mux1 and the 22 to select the control signal of 1 data selector Mux2 as the 1, the second configuration bit C2 selects 1 data selector Mux3 and the 52 to select the control signal of 1 data selector Mux5 as the 32, the 3rd configuration bit C3 selects 1 data selector Mux4 and the 62 to select the control signal of 1 data selector Mux6 as the 42, the 4th configuration bit C4 selects 1 data selector Mux7 and the 82 to select the control signal of 1 data selector Mux8 as the 72, the 5th configuration bit C5 selects 1 data selector Mux9 and the 10 to select the control signal of 1 data selector Mux10 as the 92.
Further, the described the 1 selects 1 data selector Mux1, the 22 to select 1 data selector Mux2, the 32 to select 1 data selector Mux3, the 42 to select 1 data selector Mux4, the 52 to select 1 data selector Mux5 and the 62 to select 1 data selector Mux6, forms switching network; The described the 72 selects 1 data selector Mux7, the 82 to select 1 data selector Mux8, the 92 to select 1 data selector Mux9 and the 10 to select 1 data selector Mux10, forms permutation network.
Further, first input bit of described preposition switching network, does not need to connect corresponding 2 and selects 1 data selector, is directly connected with first order bit permutation sub-network; Last input bit of preposition switching network, does not need to connect corresponding 2 and selects 1 data selector, is directly connected with afterbody bit permutation sub-network.
Meanwhile, another technical scheme that the present invention adopts is: a kind of configurable bit permutation operation method, comprises the following steps:
A, according to classification recurrence mutual exclusion configuration requirement, entire cascaded network is divided into each sub-network of different stage;
B, according to classification recurrence mutual exclusion configuration requirement, first order network is configured, until all do not comprise sub-network in entire cascaded network, entire cascaded network configuration completes.
Further, in step b, the operation that the first order network in networks at different levels is configured, specifically comprises the following steps:
B1, the input bit of determining first order network and output bit;
B2, by described input bit and output bit, according to corresponding relation, pairing generates mutual exclusion bit pair; Meanwhile, described input bit and output bit are divided into two mutual exclusion set;
B3, two mutual exclusion set after dividing are judged:
If comprise mutual exclusion bit pair in the arbitrary set after dividing, again described input bit and output bit are divided into two mutual exclusion set, until in the arbitrary set after dividing, all do not comprise mutual exclusion bit to time, generate the configuration information of first order network;
B4, to generating the first order network of configuration information, judge:
If generated in the network at the corresponding levels of configuration information, comprise sub-network, according to the configuration information having generated, calculate the input bit and output bit that obtain two sub-networks that network packet at the corresponding levels contains;
B5, return to step b2, according to identical classification recurrence mutual exclusion configuration requirement, two sub-networks that respectively network packet at the corresponding levels contained are configured; Until do not comprise sub-network in network at the corresponding levels, network configuration at the corresponding levels completes.
Configurable bit replacement computation system and the method for various embodiments of the present invention, because this system comprises routing algorithm unit, configuration information memory and the bit permutation arithmetic element connecting successively, wherein: routing algorithm unit, be used for according to default network configuration principle, generate after corresponding configuration information, described configuration information is sent to configuration information memory; Configuration information memory, the configuration information sending for receiving described routing algorithm unit, stores, and described configuration information is sent to bit permutation arithmetic element; Bit permutation arithmetic element, the configuration information sending for receiving described configuration information memory, is configured corresponding network; After having configured, the bit permutation arithmetic element having configured, processes according to displacement input data, generates displacement Output rusults; Basic bit in-place computation subelement can be expanded with the cascade network of cross exchanged, can be generated the bit permutation arithmetic element of any bit wide; The recurrence mutual exclusion placement algorithm that adopts classification, the networks at different levels that entire cascaded network are divided into different stage are configured, simple to operate; Thereby can overcome complex structure in prior art, circuit, realize that area is large, placement algorithm is complicated, autgmentability is poor with replacement process, the defect of blocking easily occurs,, circuit simple with implementation structure realized little, the easy expansion of area, the configurable and simple advantage of placement algorithm.
Other features and advantages of the present invention will be set forth in the following description, and, partly from specification, become apparent, or understand by implementing the present invention.Object of the present invention and other advantages can be realized and be obtained by specifically noted structure in the specification write, claims and accompanying drawing.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, for explaining the present invention, is not construed as limiting the invention together with embodiments of the present invention.In the accompanying drawings:
Fig. 1 is configurable bit replacement computation system operation principle schematic diagram according to the present invention;
Fig. 2 is 4 * 4 subtended network configuration schematic diagrames of the configurable bit replacement computation system according to the present invention;
Fig. 3 and Fig. 4 are 8 * 8 subtended network configuration schematic diagrames of the configurable bit replacement computation system according to the present invention;
Fig. 5 a and Fig. 5 b are the schematic flow sheet of the configurable bit permutation operation method according to the present invention.
By reference to the accompanying drawings, in the embodiment of the present invention, Reference numeral is as follows:
1-routing algorithm unit; 2-configuration information memory; 3-bit permutation arithmetic element.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.
system embodiment
According to the embodiment of the present invention, as Figure 1-Figure 4, provide a kind of configurable bit replacement computation system.
As shown in Figure 1, the configurable bit replacement computation system of the present embodiment, comprise the routing algorithm unit, the configuration information memory 2 and bit permutation arithmetic element 3 that connect successively, wherein: routing algorithm unit 1, be used for according to default network configuration principle, generate after corresponding configuration information, configuration information is sent to configuration information memory 2; Configuration information memory 2, the configuration information sending for RX path selection algorithm unit 1, stores, and configuration information is sent to bit permutation arithmetic element 3; Bit permutation arithmetic element 3, the configuration information sending for receiving configuration information memory 2, is configured corresponding network; After having configured, the bit permutation arithmetic element 3 having configured, processes according to displacement input data, generates displacement Output rusults.
Here, equipping rules, default network configuration principle, is specifically as follows: in every one-level network configuration, respectively input and output bit is divided into groups, mutual exclusion bit centering bit is not on the same group.
Particularly, above-mentioned bit permutation arithmetic element 3, comprising can arbitrary extension and the multistage basic bit in-place computation subelement that arranges of upper and lower Symmetric Composite, the cascade network that is arranged between adjacent two-stage basic bit in-place computation subelement and can cross exchanged, and the classification recurrence mutual exclusion dispensing unit for transmitting control signal to multistage basic bit in-place computation subelement according to rank; Cascade network that can cross exchanged, up-down structure full symmetric.
In above-mentioned multistage basic bit in-place computation subelement, every grade of basic bit in-place computation subelement, the switching network being equipped with about comprising and the arbitrarily permutation network of bit wide; Every grade of basic bit in-place computation subelement, according to permutation and combination rule, completes the displacement of N bit data, needs to carry out
operation; Wherein, switching network is carried out
operation, permutation network is carried out
operation.
Above-mentioned permutation network, comprises the multistage bit permutation sub-network that the identical and upper and lower symmetrical cascade of structure arranges; The upper and lower symmetric arrays of multistage bit permutation sub-network, the major network of composition place permutation network; At the front end of major network, be provided with preposition switching network; In the rear end of major network, be provided with rearmounted switching network; Preposition switching network, major network and rearmounted switching network, connect by laterally zygomorphic intersection level on line successively, forms entire cascaded network.
Here, first input bit of preposition switching network, does not need to connect corresponding 2 and selects 1 data selector, is directly connected with first order bit permutation sub-network; Last input bit of preposition switching network, does not need to connect corresponding 2 and selects 1 data selector, is directly connected with afterbody bit permutation sub-network.
In above-mentioned multistage basic bit in-place computation subelement, every grade of basic bit in-place computation subelement is 4 * 4 bit permutation operator unit; As shown in Figure 2,4 * 4 bit permutation operator unit comprise first to fourth input bit I
1, I
2, I
3with I
4, the first to ten network node, first to 10 select 1 data selector Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux8, Mux9 and Mux10, the first to five configuration bit C
1, C
2, C
3, C
4with C
5, and first to fourth output bit O
1, O
2, O
3with O
4.
In Fig. 2, the first input bit I
1, select the first input end and the 52 of 1 data selector Mux3 to select the first input end of 1 data selector Mux5 to be connected with the 32 respectively; The second input bit I
2, select the first input end and the 22 of 1 data selector Mux1 to select the first input end of 1 data selector Mux2 to be connected with the 1 respectively; The 3rd input bit I
3, select the second input and the 22 of 1 data selector Mux1 to select the second input of 1 data selector Mux2 to be connected with the 1 respectively; The 4th input bit I
4, select the second input and the 62 of 1 data selector Mux4 to select the second input of 1 data selector Mux6 to be connected with the 42 respectively.
In Fig. 2, the one 2 selects the output of 1 data selector Mux1, selects the second input and the 52 of 1 data selector Mux3 to select the second input of 1 data selector Mux5 to be connected respectively with the 32; The 22 selects the output of 1 data selector Mux2, selects the first input end and the 62 of 1 data selector Mux4 to select the first input end of 1 data selector Mux6 to be connected respectively with the 42.
In Fig. 2, the 32 selects the output of 1 data selector Mux3, selects the first input end and the 82 of 1 data selector Mux7 to select the first input end of 1 data selector Mux8 to be connected respectively with the 72; The 42 selects the output of 1 data selector Mux4, selects the second input and the 82 of 1 data selector Mux7 to select the second input of 1 data selector Mux8 to be connected respectively with the 72; The 52 selects the output of 1 data selector Mux5, selects the first input end and the 10 of 1 data selector Mux9 to select the first input end of 1 data selector Mux10 to be connected respectively with the 92; The 62 selects the output of 1 data selector Mux6, selects the second input and the 10 of 1 data selector Mux9 to select the second input of 1 data selector Mux10 to be connected respectively with the 92.
In Fig. 2, the 72 selects the output of 1 data selector Mux7, exports the first output bit O
1; The 82 selects the output of 1 data selector Mux8, exports the second output bit O
2; The 92 selects the output of 1 data selector Mux9, exports the 3rd output bit O
3; The 10 selects the output of 1 data selector Mux10, exports the 4th output bit O
4.
In Fig. 2, the first configuration bit C1 selects 1 data selector Mux1 and the 22 to select the control signal of 1 data selector Mux2 as the 1, the second configuration bit C2 selects 1 data selector Mux3 and the 52 to select the control signal of 1 data selector Mux5 as the 32, the 3rd configuration bit C3 selects 1 data selector Mux4 and the 62 to select the control signal of 1 data selector Mux6 as the 42, the 4th configuration bit C4 selects 1 data selector Mux7 and the 82 to select the control signal of 1 data selector Mux8 as the 72, the 5th configuration bit C5 selects 1 data selector Mux9 and the 10 to select the control signal of 1 data selector Mux10 as the 92.
As shown in Figure 2 and Figure 4, the above-mentioned the 1 selects 1 data selector Mux1, the 22 to select 1 data selector Mux2, the 32 to select 1 data selector Mux3, the 42 to select 1 data selector Mux4, the 52 to select 1 data selector Mux5 and the 62 to select 1 data selector Mux6, forms switching network; The 72 selects 1 data selector Mux7, the 82 to select 1 data selector Mux8, the 92 to select 1 data selector Mux9 and the 10 to select 1 data selector Mux10, forms permutation network.
Theoretical according to permutation and combination, in 4 * 4 bit permutation operator unit shown in Fig. 2, complete 4 positions and change action need
operation, left-half switching network is realized
right-hand part bit divides permutation network to realize respectively
In Fig. 3 and Fig. 4, the cascade network figure of 8 * 8 bit replacement computation systems, consists of preposition switching network, 24 * 4 bit permutation sub-networks (i.e. 4 * 4 sub-CMT bit permutation networks) and rearmounted switching network; There are 17 configuration bit: C
1, C
2, C
3, C
4, C
5, C
6, C
7, C
8, C
9, C
10, C
11, C
12, C
13, C
14, C
15, C
16with C
17, 8 input bit: I
1, I
2, I
3, I
4, I
5, I
6, I
7with I
8, 8 output bit: O
1(I
8), O
2(I
3), O
3(I
1), O
4(I
5), O
5(I
4), O
6(I
2), O
7(I
7) and O
8(I
6), in bracket, be the corresponding relation of output bit and input bit.Preposition switching network using after the exchange of 8 input bits as the input of 24 * 4 bit permutation sub-networks, the bit after 24 * 4 bit permutation sub-networks displacements is as the input of rear switching network, the output of rearmounted switching network be final structure.Theoretical according to permutation and combination, complete 8 positions and change action need
operation, in this configurable bit replacement computation system, preposition switching network and rearmounted switching network are realized
24 * 4 bit permutation sub-networks realize respectively
The configurable bit replacement computation system of above-described embodiment, based on permutation and combination Theoretical Design 4 * 4 combinatorial dual basic bit in-place computation subelements, adopt upper and lower symmetrical structure, by switching network and permutation network, connected to form; Basic bit in-place computation subelement is expanded with the cascade network of cross exchange, can be generated the bit permutation arithmetic element 3 of any bit wide; The network that the recurrence mutual exclusion placement algorithm of employing classification is divided into different stage by whole circuit network is configured, simple to operate; This configurable bit replacement computation system, simple in structure, circuit is realized little, the easy expansion of area, configurable and placement algorithm is simple, can complete the bit permutation operation of any bit wide, meet the requirement of multiple cryptographic algorithm, be applicable to various cryptographic algorithm circuit.
embodiment of the method
According to the embodiment of the present invention, a kind of configurable bit permutation operation method is provided, comprise the following steps:
A, according to classification recurrence mutual exclusion configuration requirement, entire cascaded network is divided into each sub-network of different stage;
B, according to classification recurrence mutual exclusion configuration requirement, first order network is configured, until all do not comprise sub-network in entire cascaded network, entire cascaded network configuration completes.
Further, in step b, the operation that the first order network in networks at different levels is configured, specifically comprises the following steps:
B1, the input bit of determining first order network and output bit;
B2, by input bit and output bit, according to corresponding relation, pairing generates mutual exclusion bit pair; Meanwhile, input bit and output bit are divided into two mutual exclusion set;
B3, two mutual exclusion set after dividing are judged:
If comprise mutual exclusion bit pair in the arbitrary set after dividing, again input bit and output bit are divided into two mutual exclusion set, until in the arbitrary set after dividing, all do not comprise mutual exclusion bit to time, generate the configuration information of first order network;
B4, to generating the first order network of configuration information, judge:
If generated in the network at the corresponding levels of configuration information, comprise sub-network, according to the configuration information having generated, calculate the input bit and output bit that obtain two sub-networks that network packet at the corresponding levels contains;
B5, return to step b2, according to identical classification recurrence mutual exclusion configuration requirement, two sub-networks that respectively network packet at the corresponding levels contained are configured; Until do not comprise sub-network in network at the corresponding levels, network configuration at the corresponding levels completes.
For example, in Fig. 5 a, the configurable bit permutation operation method of the present embodiment, comprises the following steps:
Step 100: initialization input bit and output bit, perform step 101;
Step 101: by the input bit after step 100 initialization and output bit, be paired into mutual exclusion bit pair, perform step 102;
Step 102: all bits (being paired into the right input bit of mutual exclusion bit and output bit) are divided into mutual exclusion set A and B, perform step 103;
Step 103: judge in set A or B whether comprise 2 right bits of same mutual exclusion, if not, perform step 104; If so, return to step 102;
Step 104: generate network configuration information at the corresponding levels, perform step 105;
Step 105: judge whether network at the corresponding levels comprises sub-network, if not, perform step 108; If so, perform step 106 or step 107;
Step 106: generate the input bit and output bit of sub-network A, and return to step 101;
Step 107: generate the input bit and output bit of sub-network B, and return to step 101;
Step 108: configured.
In step 100 to step 108, first determine input bit and the output bit of first order network, secondly will export bit and output bit according to corresponding relation pairing generation mutual exclusion bit pair, then input and output bit is divided into two mutual exclusion set A, B, A, B mutual exclusion, do not comprise same bits, then the mutual exclusion set generating judged in identity set, whether comprise mutual exclusion bit pair, if be judged to be noly, in mutual exclusion set, bit reselects; If be judged to be, be, according to the corresponding relation of bit and input and output in mutual exclusion set, generate the configuration information of first order network, then carry out the judgement whether network at the corresponding levels comprises sub-network, if be judged to be, be, with identical collocation method, sub-network is configured, if be judged to be No, has completed the configuration of whole network.
And for example, in Fig. 5 b, the configurable bit permutation operation method of the present embodiment, comprises the following steps:
Step 200: the input bit of the initialization first order 8 * 8 networks and output bit, perform step 201;
Step 201: be mutual exclusion bit pair by the input bit after step 200 initialization with output bit pairing, perform step 202;
Step 202: all bits (being paired into the right input bit of mutual exclusion bit and output bit) are divided into mutual exclusion set A and B, perform step 203;
Step 203: judge in set A or B whether comprise 2 right bits of same mutual exclusion, if not, perform step 204; If so, return to step 202;
Step 204: generate network configuration information at the corresponding levels, perform step 205;
Step 205: judge whether network at the corresponding levels comprises sub-network, if not, perform step 208; If so, perform step 206 or step 207;
Step 206: generate the input bit and output bit of the second level 4 * 4 sub-network A, return to step 201;
Step 207: generate the input bit and output bit of the second level 4 * 4 sub-network B, return to step 201;
After the bit of step 208:8 * 8, arithmetic element has configured.
In Fig. 5 b, by step 200, to step 208, can realize the placement algorithm of 8 * 8 bit permutation arithmetic element 3 circuit: need 17 configuration bit, and 34 2 are selected 1 data selector (Mux).Concrete configuration algorithm is as follows:
(1) the configuration of first order network:
Rearmounted switching network has the output bit of the Mux of identical configuration bit, is the bit of a pair of mutual exclusion, as follows:
Q
1={ O
1, O
5}={ I
8, I
4, configuration bit is C
14,
Q
2={ O
2, O
6}={ I
3, I
2, configuration bit is C
15,
Q
3={ O
3, O
7}={ I
1, I
7, configuration bit is C
16,
Q
4={ O
4, O
8}={ I
5, I
6, configuration bit is C
17;
The input bit that has the Mux of identical configuration bit in preposition switching network, if the bit of a pair of mutual exclusion is as follows:
P
2={ I
2, I
7, configuration bit is C
1,
P
3={ I
3, I
6, configuration bit is C
2,
P
4={ I
4, I
5, configuration bit is C
3;
Thus, by I
1, I
2, I
3, I
4, I
5, I
6, I
7, I
8be divided into 2 groups, require: I
1at first group, I
8at second group, there will not be the bit of a pair of mutual exclusion in any one group.
Obtain thus 2 groups of bit sets: { I
1, I
2, I
4, I
6, { I
3, I
5, I
7, I
8.{ I
1, I
2, I
4, I
6be the set of the permutated bit of the sub-arithmetic element of the first half 4 * 4 bit permutation, { I
3, I
5, I
7, I
8be the set of the permutated bit of the sub-arithmetic element of the latter half 4 * 4 bit permutation, therefore can obtain: C
1=0, C
2=1, C
3=0, C
14=1, C
15=1, C
16=0, C
17=1, first order network configuration completes;
Through judging, first order network also comprises 2 sub-arithmetic elements of 4 * 4 bit permutation, is second level network, continues configuration.
(2) the configuration of second level network:
The sub-arithmetic element of the first half 4 * 4 bit permutation is input as: I
1, I
2, I
6, I
4, be output as: I
4, I
2, I
1, I
6; The sub-arithmetic element of the latter half 4 * 4 bit permutation is input as: I
5, I
3, I
7, I
8, be output as: I
8, I
3, I
7, I
5;
Reuse identical method the configuration bit of 2 sub-arithmetic element circuits of 4 * 4 bit permutation calculated, can obtain:
C
4=0, C
5=1, C
6=1, C
7=1, C
8=0, C
9=0, C
10=1, C
11=1, C
12=1, C
13=1, complete the configuration of second level network;
Through judging, second level network has not comprised sub-network, and configuration finishes.
Final to 8 * 8 bit permutation arithmetic element 3 circuit, obtain 17 configuration bit and be: C
1=0, C
2=1, C
3=0, C
4=0, C
5=1, C
6=1, C
7=1, C
8=0, C
9=0, C
10=1, C
11=1, C
12=1, C
13=1, C
14=1, C
15=1, C
16=0, C
17=1, complete configuration, generate configuration information.
In sum, configurable bit replacement computation system and the method for various embodiments of the present invention, because this system comprises routing algorithm unit, configuration information memory and the bit permutation arithmetic element connecting successively, wherein: routing algorithm unit, be used for according to default network configuration principle, generate after corresponding configuration information, described configuration information is sent to configuration information memory; Configuration information memory, the configuration information sending for receiving described routing algorithm unit, stores, and described configuration information is sent to bit permutation arithmetic element; Bit permutation arithmetic element, the configuration information sending for receiving described configuration information memory, is configured corresponding network; After having configured, the bit permutation arithmetic element having configured, processes according to displacement input data, generates displacement Output rusults; Basic bit in-place computation subelement can be expanded with the cascade network of cross exchanged, can be generated the bit permutation arithmetic element of any bit wide; The recurrence mutual exclusion placement algorithm that adopts classification, the networks at different levels that entire cascaded network are divided into different stage are configured, simple to operate; Thereby can overcome complex structure in prior art, circuit, realize that area is large, placement algorithm is complicated, autgmentability is poor with replacement process, the defect of blocking easily occurs,, circuit simple with implementation structure realized little, the easy expansion of area, the configurable and simple advantage of placement algorithm.
Finally it should be noted that: the foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, although the present invention is had been described in detail with reference to previous embodiment, for a person skilled in the art, its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. a configurable bit replacement computation system, is characterized in that, comprises the routing algorithm unit, configuration information memory and the bit permutation arithmetic element that connect successively, wherein:
Described routing algorithm unit, for according to default network configuration principle, generates after corresponding configuration information, and described configuration information is sent to configuration information memory;
Described configuration information memory, the configuration information sending for receiving described routing algorithm unit, stores, and described configuration information is sent to bit permutation arithmetic element;
Described bit permutation arithmetic element, the configuration information sending for receiving described configuration information memory, is configured corresponding network; After having configured, the bit permutation arithmetic element having configured, processes according to displacement input data, generates displacement Output rusults;
Described bit permutation arithmetic element, comprising can arbitrary extension and the multistage basic bit in-place computation subelement that arranges of upper and lower Symmetric Composite, the cascade network that is arranged between adjacent two-stage basic bit in-place computation subelement and can cross exchanged, and the classification recurrence mutual exclusion dispensing unit for transmitting control signal to multistage basic bit in-place computation subelement according to rank; Described cascade network that can cross exchanged, up-down structure full symmetric.
2. configurable bit replacement computation system according to claim 1, is characterized in that, every grade of basic bit in-place computation subelement, the switching network being equipped with about comprising and the arbitrarily permutation network of bit wide; Every grade of basic bit in-place computation subelement, according to permutation and combination rule, completes the displacement of N bit data, needs to carry out
operation; Wherein, described switching network is carried out
operation, permutation network is carried out
operation.
3. configurable bit replacement computation system according to claim 2, is characterized in that, described permutation network comprises the multistage bit permutation sub-network that the identical and upper and lower symmetrical cascade of structure arranges; The upper and lower symmetric arrays of described multistage bit permutation sub-network, the major network of composition place permutation network;
At the front end of described major network, be provided with preposition switching network; In the rear end of major network, be provided with rearmounted switching network; Described preposition switching network, major network and rearmounted switching network, connect by laterally zygomorphic intersection level on line successively, forms entire cascaded network.
4. configurable bit replacement computation system according to claim 1, is characterized in that, every grade of basic bit in-place computation subelement is 4 * 4 bit permutation operator unit;
Described 4 * 4 bit permutation operator unit comprise first to fourth input bit I
1, I
2, I
3with I
4, the first to ten network node, first to 10 select 1 data selector Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux8, Mux9 and Mux10, the first to five configuration bit C
1, C
2, C
3, C
4with C
5, and first to fourth output bit O
1, O
2, O
3with O
4; Wherein:
Described the first input bit I
1, select the first input end and the 52 of 1 data selector Mux3 to select the first input end of 1 data selector Mux5 to be connected with the 32 respectively; The second input bit I
2, select the first input end and the 22 of 1 data selector Mux1 to select the first input end of 1 data selector Mux2 to be connected with the 1 respectively; The 3rd input bit I
3, select the second input and the 22 of 1 data selector Mux1 to select the second input of 1 data selector Mux2 to be connected with the 1 respectively; The 4th input bit I
4, select the second input and the 62 of 1 data selector Mux4 to select the second input of 1 data selector Mux6 to be connected with the 42 respectively;
The described the 1 selects the output of 1 data selector Mux1, selects the second input and the 52 of 1 data selector Mux3 to select the second input of 1 data selector Mux5 to be connected respectively with the 32; The 22 selects the output of 1 data selector Mux2, selects the first input end and the 62 of 1 data selector Mux4 to select the first input end of 1 data selector Mux6 to be connected respectively with the 42;
The described the 32 selects the output of 1 data selector Mux3, selects the first input end and the 82 of 1 data selector Mux7 to select the first input end of 1 data selector Mux8 to be connected respectively with the 72; The 42 selects the output of 1 data selector Mux4, selects the second input and the 82 of 1 data selector Mux7 to select the second input of 1 data selector Mux8 to be connected respectively with the 72; The 52 selects the output of 1 data selector Mux5, selects the first input end and the 10 of 1 data selector Mux9 to select the first input end of 1 data selector Mux10 to be connected respectively with the 92; The 62 selects the output of 1 data selector Mux6, selects the second input and the 10 of 1 data selector Mux9 to select the second input of 1 data selector Mux10 to be connected respectively with the 92;
The described the 72 selects the output of 1 data selector Mux7, exports the first output bit O
1; The 82 selects the output of 1 data selector Mux8, exports the second output bit O
2; The 92 selects the output of 1 data selector Mux9, exports the 3rd output bit O
3; The 10 selects the output of 1 data selector Mux10, exports the 4th output bit O
4;
Described the first configuration bit C1 selects 1 data selector Mux1 and the 22 to select the control signal of 1 data selector Mux2 as the 1, the second configuration bit C2 selects 1 data selector Mux3 and the 52 to select the control signal of 1 data selector Mux5 as the 32, the 3rd configuration bit C3 selects 1 data selector Mux4 and the 62 to select the control signal of 1 data selector Mux6 as the 42, the 4th configuration bit C4 selects 1 data selector Mux7 and the 82 to select the control signal of 1 data selector Mux8 as the 72, the 5th configuration bit C5 selects 1 data selector Mux9 and the 10 to select the control signal of 1 data selector Mux10 as the 92.
5. configurable bit replacement computation system according to claim 4, it is characterized in that, the described the 1 selects 1 data selector Mux1, the 22 to select 1 data selector Mux2, the 32 to select 1 data selector Mux3, the 42 to select 1 data selector Mux4, the 52 to select 1 data selector Mux5 and the 62 to select 1 data selector Mux6, forms switching network; The described the 72 selects 1 data selector Mux7, the 82 to select 1 data selector Mux8, the 92 to select 1 data selector Mux9 and the 10 to select 1 data selector Mux10, forms permutation network.
6. configurable bit replacement computation system according to claim 3, is characterized in that, first input bit of described preposition switching network does not need to connect corresponding 2 and selects 1 data selector, is directly connected with first order bit permutation sub-network; Last input bit of preposition switching network, does not need to connect corresponding 2 and selects 1 data selector, is directly connected with afterbody bit permutation sub-network.
7. a configurable bit permutation operation method, is characterized in that, comprises the following steps:
A, according to classification recurrence mutual exclusion configuration requirement, entire cascaded network is divided into each sub-network of different stage;
B, according to classification recurrence mutual exclusion configuration requirement, first order network is configured, until all do not comprise sub-network in entire cascaded network, entire cascaded network configuration completes;
According to classification recurrence mutual exclusion configuration requirement, the operation that the first order network in networks at different levels is configured, specifically comprises the following steps:
B1, the input bit of determining first order network and output bit;
B2, by described input bit and output bit, according to corresponding relation, pairing generates mutual exclusion bit pair; Meanwhile, described input bit and output bit are divided into two mutual exclusion set;
B3, two mutual exclusion set after dividing are judged:
If comprise mutual exclusion bit pair in the arbitrary set after dividing, again described input bit and output bit are divided into two mutual exclusion set, until in the arbitrary set after dividing, all do not comprise mutual exclusion bit to time, generate the configuration information of first order network;
B4, to generating the first order network of configuration information, judge:
If generated in the network at the corresponding levels of configuration information, comprise sub-network, according to the configuration information having generated, calculate the input bit and output bit that obtain two sub-networks that network packet at the corresponding levels contains;
B5, return to step b2, according to identical classification recurrence mutual exclusion configuration requirement, two sub-networks that respectively network packet at the corresponding levels contained are configured; Until do not comprise sub-network in network at the corresponding levels, network configuration at the corresponding levels completes.
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| CN101014012A (en) * | 2007-02-02 | 2007-08-08 | 华为技术有限公司 | Benes network and variable length packet distributing method and equipment |
| CN101023621A (en) * | 2004-09-24 | 2007-08-22 | 塞纳普蒂克实验室有限公司 | Substitution boxes |
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