SU993477A1 - Buffer logic ttl-device - Google Patents

Description

(54) BUFFER LOGICAL TTL DEVICE

The invention relates to pulse and computer engineering and automatics, namely, buffer TTL devices that implement the function of inversions and tautology and are intended for use in counting and control computers, in data acquisition and processing systems, in various control systems management, in c & lah memory, etc

. Logic buffer TTL devices are known that perform the functions of inversion and tautology l.

Such devices are usually implemented as two series-connected TTL inverters, have low speed and constantly consume power.

The closest to the proposed technical entity is a buffer device that is disconnected in passive mode using a key from the Earth bus, which contains a key that disconnects the device from the Earth bus, the input and output stages, the latter contains an inversion unit and a tautology unit, and the tautology unit contains the first the transistor, the base of which is connected to the output of the input stage, the collector is connected to the base of the second transistor and through a resistor to the source 2.

However, the device has a low, KIM speed and noise immunity.

The purpose of the invention is to improve the noise immunity of the buffer logic TTL device.

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The goal is achieved by the fact that a buffer logic TTL device containing a key, a B5fo ddney transistor, the emitter of which is connected to the input bus, a base through, a signal system with the power line, a collector with an intermediate transistor base, the collector of which is connected to the bases of the first and second transistors and through a resistor with food bus,

20, the collector of the first transistor is connected to the first output bus, the collector of the second transistor is connected to the base of the third transistor and through a resistor to the power supply bus,

25, the collector of the third transistor is connected to the second output bus, the emitters of the first, second and third transistors are connected to the anode of the diode, the cathode of which is connected via a switch to a common bus and through the eistor to a power bus, additionally contains a diode and a switch, the emitter the intermediate transistor is connected to the anode of an additional diode, the cathode of which is connected through a parallel-connected resistor and an additional KJ | ro4 with a common bus.

The drawing shows the electrical circuit of the proposed logical device.

The emitter of transistor 1 is the input to a logic device. The vase of transistor 1 is connected via resistor 2 to power supply bus 3. The base of transistor 1 is also connected to the anode of diode 4, the cathode of which is connected to the anode of diode 5. The cathode of diode 5 is connected to the anode of diode 6, the cathode of which is connected to the anode of diode 7, the cathode of which is connected to a common bus. The collector of the transistor 1 is connected to the base of the transistor 9, and through the resistor 10 is connected to the common bus. The emitter of the transistor 9 is connected to the anode of the diode I, the cathode of which is connected to the key 12, and also through a resistor 13 to the common bus 8. The second end of the key 12 is connected to the common bus8. The collector of the transistor 9 is connected via a resistor 14 to the power supply bus 3, and is also connected to the bases of the transistors 15 and 16. The collector of the transistor 16 is an output of the device that implements the function of tautology. The emitter of transistor 16 is connected to the anode of diode 17. The collector of transistor 15 is connected through a resistor 18 to the power supply bus 3 and through a resistor 19 to a common bus 8, as well as to the base of transistor 20, the emitter of transistor 15 and the emitter of transistor 20 are connected to the emitter of transistor 16, The collector of the transistor 20 is a device output implementing the inversion function. The cathode of the diode 17 is connected to the key 21, and also connected to the base of the two emitter transistor 22 and through a resistor 23 to the power supply bus 3. The second end of the key 21 is connected to a common bus. 8. The first emitter of transistor 22 is connected to the collector of transistor 16, the second to the collector of transistor 20, the collector of transistor 22 is connected to power supply bus 3. The collector of transistor 20 is connected via resistor 24 to power supply bus 3, the collector of transistor 16 is connected through resistor 25 with bus 3 power.

The device works as follows.

The cathode potential of diode 11 is close to the potential of the common bus S with open keys 12 and 21 and with a single signal at the input of the device is determined by the potential at the base of transistor 1, which is limited

diode circuit (diodes 4 - 7). The transistor 9, with open-ended switches 12 and 21 and a single signal at the input of the device, is located at the boundary of the conducting state and

cutoff and transmits a small current limited by a large resistor 13, therefore, after switching on the keys 12 and 21, the transistor 9 immediately goes into the conducting state,

o in contrast to transistors 15 and 16, which, with open keys 12 and 21, are in the cut-off state, since the potential on the diode 17 cathode is equal to the potential of the power supply bus 3,

5 Potential at the collector of the transistor 9 and, accordingly, the potentials at the ba-. The Z15 and 16 transistors begin to decrease. Because of this, transistors 15 and 16 remain in the state of the cutoff research institute, despite the reduction in

the potential of their emitters, and the transistor 20 transitions to the conducting state. Resistors 18 and 19 are out of itself a voltage divider and with open keys 12 and 21 provide a potential based on transistor 20 less than the potential based on transistor 15. Therefore, when the input signal of the device is zero, after the keys 12 and 21 are closed, transistor 9 remains in the cutoff state, and in nepBSTO, the transistors .15 and 16 turn into conductive state. As a result, the potential at the collector of transistor 15 and respectively at the base of transistor 20 decreases - and the transistor 20 remains in cutoff state, despite the decrease in e potential. on its emitter. Resistors 24 and 25 provide

0 output current unit output. The transistor 22 provides a large output current after it is turned off, nor the switches 12 and 21 needed to charge a large capacity load.

5 Resistor 10 reduces the potential of the base transistor 9 with a single input signal, the increase of which is due to capacitive currents after switching off. The keys are 12 and 21.

Claims (2)

1.Valiev KD, Orlikovsky A.A. Semiconductor memory integrated circuits on bipolar transistor structures, M., Sovetskoy raSh, 1979, p. 229, ris.7.21. 2. The patent of France 2373124, cl. G 11 C 17/06, 1979.,