SU982012A1 - Device for smoothing periodic random signals - Google Patents

Description

The invention relates to computing, in particular for processing digital measurement information, and can also be used in the study of periodic signals received in a mixture with noise.

A device is known that contains an analog-code converter, an iriod counter, a time interval counter, an analysis result counter, a division device, valve assemblies, a reversible counter, triggers, coincidence circuits, an inverter, a delay element l.

However, this device can only partially solve the problem of smoothing periodic noisy signals, while not providing the possibility of recording and reproducing the form of the signal under study.

Closest to the invention is a device comprising a control unit, triggers, a generator, an AND element, memory registers, a counter, a comparison circuit, an adder and a switch, the first input of the adder being connected to the output of the first register, the generator output being connected to the input of the AND element control unit

connected to the inputs of the first and second triggers, the control inputs of the first register, the switch and the counter whose output is connected to the input of the comparison circuit, the output of the comparison circuit is connected to the input of the first trigger and the control output of the device, the output of the second register is the input of the switch ( 12.

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The disadvantage of this device is the low reproduction accuracy of periodic random signals.

The purpose of the invention is to improve accuracy.

15

This goal is achieved by the fact that in the device containing the control unit, the first output of which is connected to the first inputs of the trigger and the first counter, the switch, the first

The 20th input of which is connected to the output of the first register, the second register, the output of which is connected to the first input of the adder, is inserted into an amplifier, an analog-to-digital converter,

25 memory block, dividing unit, binary-to-decimal converter, display unit, second and third counters, nepecTpavi-frequency frequency generator, and pulse shaper, with the amplifier output through

The tax-to-digital converter is connected to the first INPUT of the second register, the switch output is connected to

the second input of the adder, the output of which is connected to the first input of the ami block, the second input of which is connected to the second output through a second meter

control locus, the output of the memory unit is connected to the first input of the first register, the output of which is connected to the first input of the division unit, the second U input of which is connected to the first output of the first counter, the output of the memory unit via the binary code converter to the binary decimal connection with the first input of the block indications t5, the second input of which is connected to the output of the second counter, the third and fourth outputs of the control unit are connected respectively to the second inputs of the first and second registers, 20 the first generator output tunable the frequency is connected to the second inputs of the first counter and the trigger, the output of which is connected to the second input; the switch house, the second output of the tunable frequency generator 25 is connected via a pulse shaper to the input of the second counter, the third output to the first input of the control unit, the second input of which is connected to the second output of the first counter, and the control unit contains the decoder, the first and second, triggers, the element OR, pulse generator and counter,: whose input is the first input of the block, the output 35 of the counter is connected to the first input of the decoder, the output of the first trigger is directly connected to the first the input of the OR element, and through the pulse shaper - to the first input 40 of the second trigger, the output of the second trigger is connected to the second inputs of the decoder and the OR element, the second input of the second trigger is the second input. the block house, the output of the element OR is the first output of the block, the three outputs of the decoder are the second, third and fourth output of the block, respectively.

FIG. 1 shows a block diagram of a device for smoothing out periodic random signals; FIG. 2 is a block diagram of a control unit.

The proposed device contains 55 control unit 1, trigger 2, first counter 3, switch 4, first and second registers 5 and 6, adder 7, amplifier 8, analog-to-digital converter 9, memory block 10, division block 1160, binary converter 12 code in binary-decimal, f block 13 display, the second counter 14, the tunable frequency generator 15, the pulse shaper 16. 65

The control unit contains a decoder 17, the first and second triggers 18 and 19, the element OR 20, the pulse shaper 21, the counter. 22, the device also includes a third counter 23.

The principle of operation of the device is as follows.

Claims (2)

The input periodic signal U (t) received in a mixture with noise is fed to the amplifier 8, where it is normalized to the required value and transmitted to the analog-to-digital converter 9. Here the continuous signal is converted into a digital code. The sampling of the already converted signal is carried out on the second memory register 6, where the instantaneous values of the signal with the frequency fp (sweep) are stored. This frequency is generated by the tunable frequency generator 15 and is generated in the control unit 1 and fed to the second memory register b. At the initial moment of registration, the device operates in the No accumulation mode. As a consequence, the trigger 18 switches to the one state. The second pulse shaper 21 generates a differential pulse and sets the trigger 19 to the zero state. The zero potential allows the decoder 17 to pass the write pulses to the first and second registers 5 and 6 of the memory and, through the third counter 23, to the memory 10, and also keeps one of the inputs of the OR 20 element closed. The third counter 23 sets the operation mode of the memory block 10 Record. The potential of a unit coming from another output of trigger 18 is transmitted by the element OR 20 to the first counter 3 and trigger 2. This potential prevents the first counter to be counted 3 and, switching on trigger 2, keeps switch 4 closed. In this case, the output of switch 4 contains the zero code . The resulting code allows discrete samples to pass through the adder 7 directly to the memory block 10. Here, all the samples are recorded and they are alternately read in all positions respectively. The read signal information is copied to the first register 5 of the memory v and fed to the division unit 11. . Since the registration mode is initial, the unit code is removed from the output of the first counter 3, i.e. no division occurs. Therefore, information is immediately fed to the code converter 12, where the binary code is converted to binary-decimal and in this form is fed to the vertical buses of the display unit 13. The horizontal buses Eg are connected to the second counter 14, as a result of which a waveform image is formed on the screen of the display unit 13. The second counter 14 operates with a constant frequency fi (reproduction) coming from the tunable frequency generator 15 through the pulse shaper 16 .. In the initial mode, the sweep frequency fp, coming from the output of the tunable frequency generator 15, is resolved E5 by means of the counter 22 and decoder 17 by four clock cycles, I the first of which reads information from the cells of memory block 10, the second - overwrites information in the first memory register 5 for output to display unit 13, the third record of input information coming from nalogo-digital converter 9, the second register memory 6, and the fourth - recording this data in the memory unit 10. Thus, in the initial operation mode of the device, the formed signal is recorded as discrete values and is then read, while on the screen of the block. 13, an oscillogram of the traveling signal is observed. . To obtain a still, stable image on the screen, the operator using the control button changes the sweep frequency at the output of the tunable frequency generator 15, which corresponds to the equality or multiplicity of the sweep frequency and the signal frequency, then using the remote code setting device, sets the number of accumulation periods on the inputs The pre-trust setting of the first counter is 3 and includes the C accumulation mode. As a result, the trigger 18 switches to the zero state and closes the first input of the element OR 20. As a result, the output of the element OR 20 produces a zero potential, which removes the prohibition from the first counter 3 and trigger 2. The pulses of the end of each accumulation period coming from the first output of the generator tunable frequency 15, passes to the counting input of the first counter 3 and sets the trigger 2 to the output in the unit state. The switch, the torus 4 opens and the readable digital signal samples, stored during the initial registration mode, pass from the output of the first register 5 of the memory to the adder 7. Here they are added to the newly received samples spaced apart from the previous ones by exactly one or several periods of the input signal. The total values are written to the memory unit 10 at the position of the read information and stored until the end of the accumulation period. Further, the procedure for summing digital samples is repeated and the | code in the first counter 3 grows. After the code in the first counter 3 reaches the number of accumulation periods,. pre-recorded on the installation inputs of this counter, its output overflow produces a pulse, which is fed to control unit 1 on trigger 19. This pulse switches trigger 19 to one state. In this case, a single potential is transmitted to the output of the element OR 20 and blocks the first counter 3 and trigger 2, and also prohibits the passage of write pulses on the decoder 17, which enter the input of the third counter 23 and the second memory register b. The zero potential from the output of the trigger 2 closes the switch 4. The pulses from the end of the accumulation period to the counting input of the first counter 3 stop and the device automatically switches to the periodic output to the screen of the filtered signal. If it is necessary to resume the filtering process, the control unit 1 should be switched to the No accumulation mode. Thus, establishing a still image of a waveform, specifying the required number of accumulation cycles, adding together digital samples that are distributed over one or several periods of the input signal, and bringing the total signal to the input range significantly improves the accuracy of reproduction of the periodic signals received. mixed with noise. The latter can be represented by both High Uino Noise and low frequency component noise. In addition, and most importantly, digital signal processing is performed in real time, the ability to externally adjust the ratio of signal power to interference power is achieved by setting the number of accumulation cycles by the operator. Claim 1. Device for smoothing periodic random signals containing a control unit, the first output of which is connected to the first inputs of the trigger and the first counter, the switch, the first input of which is connected to the output of the first register, the second register, the output of which is connected to the first input of the adder, This is because, in order to improve accuracy, an amplifier, an analog-digital converter, a memory unit, a division unit, a binary-to-binary binary converter, a display unit, swarm and third counters, tunable frequency generator and pulse generator, the amplifier output being connected via an analog-to-digital converter to the first input of the second register, the switch commutator output connected to the second input of the adder, the output of which is connected to the first memory input, the second input of which is connected to the second output of the control unit , the output of the memory unit is connected to the first input of the first register, the output of which is connected to the first input of the division unit, the second input of the division unit is connected to the first output of the first counter, the output of the division unit A binary-to-binary converter is connected to the first input of the display unit, the second input of which is connected to the output of the second counter, the third and fourth outputs of the control unit are connected respectively to the second inputs of the first and second registers, the first output of the tunable frequency generator is connected to the second inputs the first counter and trigger, the trigger output is connected to the second input of the switch, the second output of the tunable frequency generator is connected via a pulse shaper to the second input the third output of the tunable frequency generator is connected to the first input of the control unit, the second input of which is connected to the second output of the first counter. 2. Device POP.1, characterized in that the control unit contains a decoder, first and second triggers, an OR element, a pulse shaper and a counter whose input is the first input of the block, the output of the counter is connected to the first input of the decoder, the output of the first trigger directly connected to the first input of the OR element, and through a pulse shaper to the first input of the second trigger, the output of the second trigger is connected to the second inputs of the decoder and the OR element, the second input of the second trigger is the second input of the block, the output The OR element is the first output of the block; the three outputs of the decoder are respectively the second, third, and fourth outputs of the block. Sources of information taken into account in the examination 1. USSR author's certificate No. 252732, cl. G 06 F 15/36, 1970. 2. USSR author's certificate No. 744599, cl. G 06 F 15/353, 1980 (prototype). .