SU978379A1 - Discrete counter transmission device - Google Patents

Description

The invention relates to data transmission. A device for transmitting discrete signals is known, comprising a keyboard unit, the outputs of which are connected to the inputs of the first and second elements OR, to one input of the storage device and to the first input of the distributor, the first output of which is connected to other inputs of the storage device whose outputs are connected to the matching 6rtoKa The corresponding input of which is (connected to the second outlet of the distributor 1). However, in a known device, the transmission speed is insufficient. The purpose of the invention is to increase the transmission speed. a unit for transmitting dysffetting signals, containing a keyboard unit, the outputs of which are connected to the inputs of the first and second elements OR, to one, the inputs of the accumulator, and to the first input of the distributor, the first output of which is connected to other inputs of the accumulator a block, the corresponding input of which is connected to the second output of the distributor, is entered a decoder, a shift register, a block of counters and a series-connected prohibition element, a code combination analyzer and a memory block, the strokes of which are connected to the additional inputs of the matching block and the accumulator, whose additional outputs are connected to the inputs of the meter block, whose outputs are connected to the second inlet and distributed to the second and third memories of the memory block, the fourth one of which is connected to the corresponding meter block input to the first the input of the distributor and with the output of the shift register, to the inputs of which are connected & the outputs of the decoder, whose inputs are connected with the same drive inputs, while the output of the first element OR It is connected to the input of the prohibition element, the second input of which is connected to the corresponding output of the power unit; .1 of the block, and the output of the second element OR is connected to the second input of the analyzer. code combinations. The drawing shows a structural electrical circuit of the proposed device. the device contains a distributor 1, a keyboard unit 2, a drive 3, a matching unit 4, elements OR 5 and О, a register. 7 shift, prohibition element 8, analyzer 9 code combinations, block 1C; memory, block 11 counters, decoder 12. The device operates as follows. In the initial state, the start-stop button 1 of the distributor 1 is turned on by the signal from the output of the shift register 7, the stop parcel is transmitted to the B line, the initial code is set in block 11 of the counters, 1 is recorded to the signal bit of memory block 1O. When the operator presses a key (for example, the register is enabled. Rus) to send a message through the element OR 5, the prohibition element 8 (the prohibition signal at the output S of the keyboard unit 2 is absent) transmits a signal to one of the outputs of the analyzer 9, which, rightly, reads memory unit register register first of all drive 3. With high-frequency clock from distributor 1, this combination rewrites Vets successively into the second, third, .. And drive 3 of the drive, freeing the first step of the drive 3 for writing A combination of code that appears at the output of the keyboard unit 2 after pressing a key. Then, when pressing the subsequent keys of the register Rus, similar information is recorded into the first storage stage, which are copied to the second, ..., at the storage stage . In the case of switching to the Numbers keys when a key is pressed that corresponds to the transmission of digital characters or numbers, a signal is received through the OR 6 element to the second input of the analyzer 9. For this signal, the analyzer 9, Fired, reads from the memory block 1O the register combination of the Digits first of the drive 3. In the case of pressing the key of the keys with buchennye characters located on the digital register (W, Scht.d.), OR 5 and the prohibition element 8 sends a signal to one of the outputs of the analyzer 9, which reads from memory block 10 to drive 3 a register combus. Rus. To transmit a Latin player's combination of a switch (not shown), the Rus-Lat operator translates to the Lat position, the Lat Register register from the output of the keyboard combinator of the keyboard unit 2 will be recorded first of drive 3. At the same time, from the output of the keyboard block, the prohibition signal is sent to the prohibition element B, thereby preventing reading of the register combination Rus from the memory block 10 when pressing the keys of the alphabetic register, for transmitting the Latin alphabet combinations. When switching from the Lat register to the Digit register, the Digit register combination is automatically transferred to the line. When switching from the Lat register to the Rus register, the Rus-Lat switch is manually switched to the Rus position (by pressing a button). In this case, a signal is removed from the output f of the keyboard unit 2 and the prohibition element opens for passing the signal ha one of the OUTPUTS of the analyzer 9. Next, the circuit operates according to the previously described algorithm. When the key is pressed by the operator, the code combinations are recorded in the first stage of the accumulator 3, which is transmitted to the accumulator by high-frequency ticks. Simultaneously, block 11 counts the combinations filled by the accumulator 3. The (U1 -2) th stage of the accumulator 3 of the first combination (in the considered case the combination of Rus) from the output of the block 11 sends a signal to the distributor 1 and to the input of the memory block 10. With this signal, in the distributor 1, the start-stop unit is turned on and the starting package is transmitted to the line through the matching unit 4. If there is 1 in the signal bit of memory block 10, the service indication of the beginning of the message is transmitted to the line via matching unit 4, and the content of the signal bit is erased. After recording the first combination in the Cth stage (in the considered case, the Rus combination), a signal is given from the output of block 11 to the input of block 10 of memory. The signal from block 11 of the block

10 memory through the matching unit 4 the service start of the block is counted in a line, and the service feature the end of the block from the memory block 10 is recorded first of the drive 5. So, the starting package will be transferred to the line through the matching unit 4 The beginning of the message, the beginning of the block, the information combinations of the block and the service sign are the 10th sign of the end of block.

At the time of termination of the service feature. The end of the block is again signaled to the input of the block of memory 10 from the output of block 11, if 1S has the next data block recorded to drive 3. A data block with service attributes Start of the block and End of the block will be transmitted to the line. At the end of the message, the operator dials on the keyboard the service indication End 20 of the message (NNNN), which is highlighted by the search circuit, which includes shift register 7 and decipher 12. In the process of searching for the sign End of message (NNNN), when the 25 sign N is received, The output of the decoder 12 is a signal that leads to the recording of state 1 in the first bit of the 3-bit shift register 7. Signal output register 7eo

A shift is possible when taking another four N. For any smaller number of received N digits, the contents of the shift register 7 are erased.

From the output of the shift register 7, a start signal is supplied to the distributor 1, by which the start-stop unit is turned on, and a stop package is transmitted to the line via the matching unit 4. At the same time, this signal is set to Q

Setting the start code in block 11 is written to 1 in the signal bit of memory block 10.

The analysis shows that when using the proposed device, the operator's performance and water velocity are in a computer. can be increased compared with the prototype (with the dinac structures transmitted

information and channel data rates) is approximately

1.5-2 times.

Claims (1)

1. USSR author's certificate No. 379986, cl. H O4L 13 / O2, 1971 (prototype).