SU978035A1 - Ultrasonic flaw detector - Google Patents

Description

The invention relates to non-destructive ultrasonic testing and can be used to control materials and products.

Known ultrasonic flaw detector containing a synchronizer., A strobe pulse shaper, a generator of ultrasonic oscillations, a transducer, a preamplifier, an amplifier and a detector, a second amplifier, a comparator and a C1 recorder,

The disadvantage of the known flaw detector is the low reliability of the control, since the dynamic range of the measured amplitude is small.

The closest to the invention in technical essence and the achieved result is an ultrasonic flaw detector containing a synchronizer connected in series, the output of which is connected to the input of the strobe pulse shaper, excitation pulse generator, transducer, preamplifier, attenuator, first

amplifier and detector, second amplifier, analog-to-digital converter (ADC) and recorder 2,

A disadvantage of the known flaw detector is the low reliability of the control, since repeated repeated repetition of the measured signal is necessary to determine its amplitude, in addition, the dynamic range of the measured amplitude is small, since it is determined by the range of the amplifier and detector.

The purpose of the invention is to increase the reliability of the control,

The goal is achieved by the fact that the ultrasonic flaw detector provides wives with a delay line connected between the preamplifier and the attenuator, a peak detector connected between the detector and the ADC, the first shift register connected between the ADC and the register, connected in series between the strobe pulse shaper and the ODN-vibrator, and the register is connected in series with the stub pulse generator and connected in series the output of which is connected to the second input of the first shift register, by a trigger and the first circuit I, connected successively by a clock pulse generator, whose input is connected It is not connected with the trigger output, the second AND circuit, the output of which is connected to the third input of the first shift register, the conversion unit and the reversible counter, the output of which is connected to the second inputs of the AND circuits connected in series with a digital-to-analog converter (DAC), comparator, the second input which is connected to the output of the second amplifier, a pulse expander, the output of which is connected to the second detector input, and an OR circuit, the output of which is connected to the second inputs of the peak detector and ALlflj with the second shift register, whose input is the output of the synchronizer is connected to the second inputs of the trigger, the reversible counter and the OR circuit, the output of the pulse extender is connected to the third input of the reversible counter, and the output of the preamplifier is connected to the input of the second amplifier; FIG. 1 is a block diagram of an ultrasonic flaw detector. The ultrasonic flaw detector contains a synchronizer 1 connected in series, the output of which is connected to the input of the strobe pulse generator 2, a pulse generator 3 and a converter, a preamplifier 5 attenuator 6, a first amplifier 7 and a detector 8, a second amplifier 9, ADC 10 and a recorder 11 In addition, the ultrasonic flaw detector contains a delay line 12 connected between the preamplifier 5 and the attenuator 6, the peak detector 13; connected between the detector 8 and the ADC 10, the first register AND shift included between the ADC 10 and the recorder 11, connected in series between the strobe pulse generator 2 and the recorder 11, the one-shot 15 whose output is connected to the second input of the first register 14 of the shift, trigger 16 and the first circuit 17 is connected in series to a clock pulse generator 18, the input of which is connected to the trigger output 16, second circuit 19, the output of which is connected to the third input of the first shift register 1, recalculation unit 20, and pe 1 counter 21, the output to Secondly connected to the second inputs of the circuits I 7 and 19, successively soy, qi; - Ennier DAC 22 and comparator 2.3, the second BCSD of which is connected to the output of the second amplifier 9, the scatter indicator 2 and; -n pulses, the output of which is connected to the secondary input the detector 8, and the OR circuit 25s, the output of which is connected to its inputs of the pixel detector i; and A / D converter 10, second register 2b:: the input of which is connected to the output of the comparator 23, and the output to the input of the DAC 22 and the control input of the attenuator 6. The output of the synchronizer 1 is connected to the second inputs of the trigger 16, the reversing counter 21, and the OR circuit 25. The output of the expander 24 pulses connected to the third input of the reversible counter 21, and the output of the preamplifier 5 is connected to the input of the second amplifier 9 Ultrasonic flaw detector works as follows. Synchronizer 1 starts simultaneously a generator of 3 excitation pulses, a driver of 2 strobe pulses, a reversible counter 21 and OR circuit 25 for resetting the peak detector 13 and the A / D converter 10. The sounding pulse from the output of the generator 3 of excitation pulses goes to the converter. The signals reflected from the defect are then taken by converter k, converted to electrical, amplified by preamplifier 5, and fed after amplification by amplifier 9 to the first input of the comparator 23 and delayed by delay line 12 to the input of the controlled attenuator 6. The delay time of delay line 12 should be longer the time required for the discharge and subsequent charge of the peak detector 13 and the switching time of all devices at the time of the comparator 23 triggered. From the output of the controlled attenuator 6, the signals go to the first amplifier 7, Next, the detector 8 and in the form of a video signal to the peak detector 13. The voltage from the peak detector 13 is converted into a digital code by the A / D converter 10, transmitted to the first shift register 1 and the last output from the last one to the recorder 11. The falling edge of the strobe the pulse of the control zone with the strobe pulse generator 2 starts the one-shot 15, the pulse duration of which must be 597 not less than the conversion time in the ADC 10 voltage from the output of the peak detector 13. The falling edge of this pulse records information and with the A / D converter 10 into the first register 1 shift ga, trigger 1b is triggered. The trigger 1b is reset by a pulse from the synchronizer output 1. A pulse from the trigger 1b is fed to the first AND 17 circuit, and if a signal coinciding with this pulse appears at the other last input, then the output of the first AND 17 circuit is a signal permitting recording information to the recorder 11 The pulse from the trigger 16 emits a pulse 18 clock pulses. Clock pulses are generated with a phase r: p | - | To the start of the output lmpulg.z with trigger 16 ta; Jto do by entering; .gz second schehenu; and shifting information nz they proceeded to the first register, k, the second, fourth, etc., half-wave half-waves. At the second input of the comparator 23, the initial voltage of the DAC 22 is set to its initial voltage so that the signal is below the upper point of the linear region of the gain characteristic of amplifier 7 and detector 8 and below the upper point of the linear range of the peak detector 13- If the ultrasonic signal is small (below the indicated upper points of linearity), then the controlled attenuator 6 passes it without slackening after a time determined by the delay line 12 and at the recorder 11 when the signal appears from the first circuit 17 that allows recording, in digital code, the amplitude In this case, the signal from the output of amplifier 9 is lower than the initial voltage from the DAC 22. If the signal is large (above the indicated upper linearity points), then from the output of amplifier 9 the signal will exceed the initial voltage from the DAC 22, comparator 23 the pulse from its output goes to the shift input of the second shift register 26 and to the 2k expander to completely reset the detector 8 and through the OR circuit 25 of the ADC peak detector 10. In the second shift register 2b, a pre-synchronization pulse or any other pulse before the start of the strobe pulse in the control zone, information is recorded that provides the maximum transfer ratio of the attenuator 6. When a signal appears at the shift input of the second shift register 2b 5, the recorded information is moved, and at its output, the code that goes to the DAC 22 converts to the operation of the comparator 23, is so many times greater than the initial voltage at the output of the D / A converter 22, in a collapse the attenuation level of the controlled attenuator 6 is selected, and to the control input of the controlled attenuator 6. At the same time, the output signal de controlled attenuator 6 umenshits as many times as the selected level of attenuation and the attenuator (e.g., 4). Trigger the comparator 23 and increase the attenuation of the controlled. the attenuator 6 will occur until the voltage at the output of the DAC 22 is higher than the signal at the output of the second amplifier 9. Each time the comparator 23 triggers, a pulse arrives at the direct count input of the reversing counter 21 and the detector 13, the peak detector 13, is reset. and ADC 10. After these faults, the output of ADC 10 sets the code of the signal attenuated m times, where m is the number of operations of the comparator 23. When 2 pulses arrive from the expander at the direct count input of the reversing counter 21 at its output, counting by a Wits pulse, allowing signals to pass through the AND 17 19. circuit. This allowing pulse lasts for as long as the clock pulses from the generator are 18 clocks that passed through the 19 And circuit and the recalculation unit 20 to the counting input of the reversing counter 2-1, They are not equal in quantity with the number of pulses at the input of the direct count of the reversible counter 21. Recalculation unit 20 is necessary if the attenuation level of the attenuator 6 is not equal to two (about 2). If the attenuation stage of the attenuator 6 is equal to two, then the clock pulses from the generator 18 clock pulses must be received through the circuit 19 AND and the recalculation unit 20 to the countdown input of the reversible counter 21 without changing their number. If, for example, the attenuation level of the attenuator 6 is four (a k), then the countdown input of the reversible counter 21 must receive two times fewer pulses than the number of times the comparator 23 triggers. Clock pulses from the generator 18

clock pulses through the circuit And 19 also arrive at the input of the shift of the first register Il of the shift, producing a shift of the recorded information by as many m bits as many times the comparator 23 triggered, i.e., the operation of multiplying the amplitude code measured by the ADC 10 by the division ratio of the controlled attenuator 6 and, by that, providing a representation of the true value of the measured amplitude. Thus, in the first shift register It, the amplitude of the ultrasonic signal will be restored, the attenuation of which was performed by the attenuator 6 being controlled.

Consequently, depending on the maximum amplitude of the ultrasonic signal entering the input of amplifier 7, the attenuation coefficient of the controlled attenuator 6 is automatically reduced a certain number of times so that the signal at the input of the A / D converter 10 is always within its dynamic range. Shifting the first register 14. Shifting by the attenuation coefficient of the attenuator 6 makes it possible to determine the true value of the amplitude. Thus, the dynamic measurement range of the signal is increased by as many times as its controlled attenuator 6 weakens.

The described invention allows for highly reliable inspection of products.

4 formula of invention

An ultrasonic flaw detector containing a synchronizer connected in series, the output of which is connected to the input of a strobe pulse shaper, a pulse generator, a transducer, a preamplifier, an attenuator, a first amplifier and

a detector, a second amplifier, an analog-to-digital converter (ADC) and a recorder, characterized in that, in order to increase the reliability of the control, it is equipped with a delay line connected between the preamplifier and the attenuator, the peak detector connected between the detector and the ADC, the first shift register, connected between the ADC and the recorder, connected in series between the strobe pulse shaper and the one-shot recorder, the output of which is connected to the second input of the first shift register, a trigger and the first circuit And, connected in series by a clock pulse generator, whose input is connected to the trigger output, a second And circuit, the output of which is connected to the third input of the first shift register, a conversion unit, and a reversible counter, the output of which is connected to the second inputs of the And circuits, connected in series with a digital-to-analog converter (D / A) , a comparator, the second input of which is connected to the output of the second amplifier, a pulse expander, the output of which is connected to the second inputs of the peak detector and the ADC, the second shift register, the input is connected to the comparator output, and the output is connected to the DAC input and the attenuator control input, the synchronizer output is connected to the second trigger inputs, the reversing counter and the OR circuit, the output of the pulse extender is connected to the third reversible counter input, and the preamplifier output is connected to the input second amplifier.

Sources of information taken into account in the examination

1. USSR author's certificate number, class, G 01 N 29/04, 1974.

2. Defectoscopy, 1978, No. 9, p. 97-99 (prototype).

Claims (1)

Claim An ultrasonic flaw detector containing a synchronizer connected in series, the output of which is connected to the input of a strobe pulse generator, an exciting pulse generator, a converter, a preamplifier, an attenuator, a first amplifier and detector, a second amplifier, and an analog-to-digital converter (ADC), and pfe recorder, characterized in that, in order to increase the reliability of control, it is equipped with a delay line connected between the preamplifier and attenuator, a peak detector connected between the detector and the ADC, the first a shift circuit connected between the ADC and the recorder, connected in series between the strobe driver and the one-shot recorder, the output of which is connected to the second input of the first shift register, the trigger and the first circuit I, connected in series with the clock pulse generator, the input of which is connected to the trigger output, the second circuit And, the output of which is connected to the third input of the first shift register, the conversion unit, and a reversible counter, the output of which is connected to the second inputs of the circuits And, connected by digitally-analogue converter (DAC), a comparator, the second input of which is connected to the output of the second amplifier, a pulse expander, the output of which is connected to the second inputs of the peak detector and the ADC, a second shift register, the input of which is connected to the output of the comparator, and the output to the input of the DAC and control input of the attenuator, the synchronizer output is connected to the second inputs of the trigger, the reverse counter and the OR circuit, the output of the pulse expander is connected to the third input of the reverse counter, and the preamp output is connected it is input to the second amplifier.