SU970428A2 - Device for evaluating truth of measurement results - Google Patents

Description

The invention relates to automation, computing and measuring technology, can be used B information-measuring systems for the operational verification of receiving information. According to the main author. St. 739618, a device for evaluating the reliability of measurement results is known, comprising a unit for determining the expectation and a controllable delay unit, the first inputs of which are combined and connected to the measurement input of the device, the first sum of the input is connected to the first input of the division unit, the second accumulator whose output is connected to the first input of the multiplier, the memory block, the output of which is connected to the second input of the multiplier, the output of the multiplier is connected to the second input of the division unit, the output of which is connected to the output of the device control unit, the first output which is connected to the second input of the controllable delay unit, is connected to the input of the delay unit, the frequency divider, the first and second absolute difference determination units, the device synchronization input is connected to the first input of the frequency divider, the first output which is connected to the fjpeTb input of the division unit, the second output of the frequency divider is connected to the second input of the expectation unit, the output of which is connected to the first input of the first absolute difference determination unit, the output the controllable delay unit is connected to the first input of the second absolute difference determination unit, the output of which is connected to the first input of the first adder, the output of the absolute difference determination unit is connected to the first input of the second adder, the third output of the frequency divider is connected to the second inputs of the first and second adders, the output of the block the delay is connected to the second input of the absolute difference determination unit; the fourth output of the frequency divider is connected to the third inputs of the first and second absolute difference determination units and, the second output of the control unit is connected to the second input of the frequency divider. The device allows one to establish the fact of the presence or absence of a random low frequency component (trend) in the process under study and change the algorithm for processing the received information in accordance with the results of the analysis. At the same time, in order to increase the credibility of the hypothesis of the absence or presence of a systematic shift in the measurement results, distorted by abnormal errors, the anomalous measurement results are partially compensated for in the device when estimating the average error, the critical error. The drawback of the device lies in the absence of current control over the intensity of anomalous measurement errors and the impossibility of completely eliminating their influence on the results of the calculation of estimates of the determined statistical characteristics. With a corresponding change in the processing algorithm of the received information, anomalous measurement results / due to the pronounced difference in their statistical characteristics from the static properties of fluctuation errors of low energy level can be easily filtered. This circumstance dictates the need to control the intensity of the appearance of anomalous measurement results. The purpose of the invention is to improve the accuracy of the device for assessing the reliability of measurement results. The goal is achieved by the fact that a median value determination unit, a second multiplier and a second dividing unit, the first and second inputs of the median value determination unit are connected to the second output of the second absolute density determination unit and the third output of the frequency divider, the output of the median value determination unit is connected to the first time of the second multiplier, the second input of which is connected to the output of the memory unit, the output of the second is cleverly connected with the second output of the device and the first input of the second dividing unit, the output of which is connected to the third input of the device, the second and third inputs of the second dividing unit are connected respectively to the second and third inputs of the first dbinie unit; . In addition, the median value determination block contains an impulse generator, memory registers, counters, a reference element, a decoder, a divider into two, the OR elements and in each processing channel — a counter, a reverse counter, an decoder, And, and a duration selector. made on adders, delay elements, amplitude discriminator, differentiating element and threshold element, the output of the first delay element is connected to the first input of the first adder, the output of which is connected to the input of amplitude razlichitel, first th output amplitude. the discriminator directly, the second output through the second delay element is connected respectively to the first and second inputs of the second adder, the output of which is connected to the first and second outputs of the duration selector through a serially connected differentiating element and threshold element, the first delay element is combined with the second input of the first adder and connected to the input of the duration selector, the first output of the selector of the duration of each processing channel is connected to the first input of the counter, the first outputs of which о is connected to the first inputs of the reversible counter, the first output of the reversible counter through the decoder is zero: connected to the first input of the first element AND, the second output to the first input of the second element AND and the corresponding input of the first element OR, the output of the pulse generator and the first element AND the first processing channel; the output of the first element AND of each previous processing channel is connected to the second inputs of the reversing, counter and the first element AND of each subsequent channel processing, the second outputs of the selectors for the duration of all processing channels are connected to the corresponding inputs of the second OR element, the output of which through the series-connected divider into two and the first counter - with the first inputs of the first memory register, the output of which is connected to the first input of the comparison element, the output of the comparison element connected to the second input of the first memory register, the first input of the second counter and the second inputs of the second elements And all processing channels whose outputs are connected to the corresponding The inputs of the decoder, the second inputs of which are connected to the outputs of the second memory register, the output of the first element OR are connected to the second input of the second counter, the output of which is connected to the second input of the comparison element, the inputs of the selectors for the duration of all processing channels are combined and connected to the first input of the detection unit the value of the median, the input of the pulse generator is combined with the inputs of the counters of all processing channels and is connected to the second input of the determination unit. the median value, the output of the decoder is connected to the output of the median value determination unit. The theoretical basis for achieving this goal is to increase the efficiency of estimates of bastardiness of measurement results with the discrete laws of the distribution of values of a distorting random process, formalization of which is admissible by the superposition of probability densities of the next type Cvr-A..Gj.) Argf ChrG / a) A , - Aa--, (1) where Hv, Gv) (l), G is one-dimensional density. Distribution of probabilities with displays (V The known device does not allow to estimate the ratio of the total error of the measurement results of the difference between fluctuation C and anoma In order to achieve the goal, the proposed device calculates the standard deviations of the following algorithms: | T | -tg. 1-t | -IV A | A h- fr-. SG. cr,) l.-A.)) 3); / Vted l ,,) bl w n-ii UD V, .., 1, WJM. N-ltltl where Y., Y. - the value of the random process under investigation; (.,) 7, „,, .. 1, L-median of a sequence of random variables (1) Cha K - difference order; . rg (± proportional ratio .V 2. VVI / nality; - statistical sample size. Fig. 1 shows: structural, block diagram of the device; Fig. 2 structural block diagram of the median value determination unit; Fig. 3; block diagram absolute difference determination; Fig. 4 - timing diagrams, explanation of the operation of duration selectors. The device contains (Fig. 1) expectation block 1, controllable delay block 2, first absolute difference block 3, delay block 4, second absolute difference determination unit 5, trans adder 6, second adder 7, first multiplier 8, memory unit 9, first division unit 10, frequency divider 11, control unit 12, median value determination unit 13, second multiplier 14, second division unit 15, synchronization input 16, measurement the input 17, the first 18 and the second IBjj outputs of the second absolute difference determination unit, the control input 19 of the median value determination unit 13, the output 20 of the median value determination unit 13, the first 21 and second 22 and third 23 outputs of the device. The median value determination unit 13 (Fig. 2) contains selectors (durations, including adders 25c and, elements | and delays, amplitude discriminators, differentiating elements and threshold elements, counters, pulse generator 33, reversible counters (, decoders, first And ZB - Zbu ;, elements OR 37 and 38, second elements AND 39.-39ts, divisor 40 into two, comparison element 41, decoder 42 values of median counters 43 and 44, memory registers 45 and 46, processing channels. the difference contains the shaper 48 PWM, ale nty NOT 49 and 5O, first elements AND 51 and 52, element OR 53, second element AND 54, pulse generator 55, PWM shaper 56. The device works as follows. Measurement results from input 17 (Fig. 1 are fed to the input of determining unit 1) mathematical expectation, where the averaging interval set by the control unit 12 through the controlled frequency divider 11 is averaged, which is a multiple of the periods of the synchronization signals. The delay time of the same measurement results in block 2 is set equal to the averaging interval. Block 3 and adder 6 implement the operations of determining the average value of the absolute differences between the current values of the measurement results and their average value. At the same time, the absolute differences between the previous and present values of the measurement results are determined in block 5 and their average value is estimated by accumulation in the adder 7 for the set averaging time. Averaging in accumulative adders is carried out by deriving the number from the higher bits of the adder, for which the averaging intervals are set to the corresponding next volumes of statistical samples N 10, where, 2,3 ... Multiplier 8 normalizes the result with the proportionality coefficient block 9. The results of the division in block 10 calculated in the first two parallel chains of the device — the statistics are equivalent on the average and in terms of dispersion dispersion to the classical Abbe criterion and can be used olzovats dl. test the hypothesis of the absence of a systematic shift in the measurement results.

Blocks 3 and 5 for determining the absolute difference (Fig. 3) work in the following IM way;

The delayed and unprotected signals about a random process are fed to the inputs of the formers 48, 56 latitudes of the no-modulated pulses (WITCH). The generated PWM pulses with the back edge modulation are inverted by the elements NOT. 49 and 50 into PWM pulses with front-edge modulation and fed to elements 51 and 52, to the second inputs of which non-inverted PWM pulses are fed from drivers 48 and 56, respectively. At the output of elements And 51 and 52, PWM pulses are formed, corresponding in duration to the difference between the selected values of the random process under study. The formed pulses, after their reduction into a single stream by the element OR 53, represent the absolute differences between the values of the random process and undergo transformations in block 13 to determine the separation of the median value and in the analog-code converter consisting of the And 54 and 1 elements of the generator 55 counting pulses.

The median value determination block 13 works as follows.

The PWM signals from the output 18 of the absolute difference determination unit 5, carrying information about the absolute values of the differences between the selected values of the random process, are fed to the inputs of the duration selectors, the outputs of which generate signals of coincidence in the duration of the incoming pulses with the selectors 24 installed in each. -24 time intervals t; , -1G2. fhz. The time interval values are given by the delay times of the incoming signal in the elements and equal to

    . respectively. The generated pulses (Fig. 4g) are counted by counters for a set interval of averaging, determined by the pulse frequency at the output 19 of the frequency divider 11. At the end of the next interval averaging the results of the calculation

The coincidence pulses of the duration of the PWM signals from the output 18 with the time intervals set are rewritten in parallel binary code into reversible counters.

5 The counters are then released to count the coincidence pulses in the new static sample. On subtractive inputs of reversible counters 34.-34j. reading is coming

0 pulses from the generator 33 pulses. With the arrival of a read pulse, the number recorded in the reversible counter 34 decreases the unit value. With every decrease by one

5 impulse, which made the connection, goes to the corresponding input of the element OR 37.

In this case, the read pulses to the subsequent reversible counter 34

0 arrives only after reading the number, for: written in the previous one.

The reading of the number written to the reversible counter 34j is performed until a signal indicating the end of the reading does not appear at the output of the corresponding decoder 35, j zero. With the appearance of the read end signal, the corresponding element is hidden

0 and 36, allowing the reading of the number written in the next j + 1st reversing counter. Read pulses in the amount corresponding to those recorded in reversible counters

5 to the numbers received through the element OR 37 to the input of the counter 44. Moreover, the accumulation of pulses in the counter 44 will take place until the number recorded in it is equal to the half sum of all coincidence pulses passed through the element OR 38 accumulated in the counter 43 pulses and rewritten in the second register 46 memory. At the moment of equality of numbers in the counter 44- and the second register 46

5 of the memory at the output of the comparison element 41, according to a potential that opens the element 1 of the I 39 39,. The signal is given at that input of the decoder of 42 values of the median, the sequence number of which coincides with

Claims (2)

the serial number of the processing channel 47 with a signal delay time, equal to HbiMTT ggj, where Tg is the median value of the probability density distribution of the duration of the PWM signals. When a signal appears at the j-oM input of the decoder of 42 median values, the output of the corresponding median value from the jth cell of the first memory register 45 is permitted. The numerical values (values stored in memory cells of memory register 45 are determined by the corresponding time intervals of the signals of selectors 24 through 24). The signals at the output of the comparison element 41 are reset to the initial zero state K + 2-nd counter 4 and second memory register 46 and is ready to accumulate and memorize data on a new statistical sample. I The work of selectors on duration is as follows. The converted random process from output 18 ,, (Fig. 4) of the second unit 5 for determining the absolute difference The spins go directly to the combined second inputs of the first adders through delay elements in which the incoming signal from the PWM is delayed and inverted (Fig. 4a). The delay times t, .Ts in channels 47.-47 | are different and are chosen according to the overlap the range of random variation in the duration of the pulse sequence under investigation. The number of channels 47–7, the processing is determined by the overlapping range and established by the differential corridor. The results of the first summation (Fig. 4b) are divided in amplitude discriminators 29., - 29, by zero level into positive and negative components. In this case, the positive component is delayed in the second delay elements, which are identical in delay time to the corresponding first delay elements by time T, tr, jL Sc. As a result of the operations performed and repeated summation in the second adders of the negative pulse sequence with the delayed positive (Fig. 4c, d, e) voltage drops + M-M are formed at those times when the pulse duration of the random process is equal to twice the delay time t 2 in the corresponding processing channel. When differentiating the results of the second summation of differentiating elements (Fig. 4e), conditions are created for the selection by limiting in the threshold elements of the impulses the appearance of values of a random process and the corresponding discharge histogram of the distribution of PWM signals (Fig. 4g). The proposed device favorably differs from the known devices by the possibility of completely eliminating the distorting effect of anomalous errors on the results of statistical processing of measurements, which makes it possible to determine the intensity of anomalous measurement results, i.e. is more accurate. Claim 1. Device for assessing the reliability of measurement results according to ed. St. No. 739618, Differing in that, in order to improve accuracy, a median value determination unit, a second multiplier, and a second division unit, the first and, are introduced into it. the second inputs of the median, diana determination unit are connected respectively to the second output of the second absolute difference determination unit and the third output of the frequency divider, the output of the median value determination unit is connected to the first input of the second multiplier, the second input of which is connected to the output of the memory unit, the second output the multiplier is connected to the second output of the device and the first input of the second dividing unit, the output of which is connected to the third output of the device, the second and third inputs of the second dividing unit are connected correspondingly It is known with the second and third inputs of the first division block. 2. A device according to claim 1, characterized in that the median value determining unit comprises a pulse generator, memory registers, counters, a reference element, a decoder, a divider into two, OR elements and in each processing channel a counter, a reversible counter, a decoder zero, And elements and duration selector, executed on adders, delay elements, amplitude discriminator, differentiating element and threshold element, the output of the first delay element is connected to the first input of the first adder, the output of which is connected to the -amp The effective discriminator, the first output of the amplitude discriminator directly, the second output through the second delay element are connected respectively to the first and second inputs of the second adder, the output of which is connected to the first and second outputs of the duration selector through serially connected differentiating element and threshold element, the second input of the first adder and is connected to the input of the duration selector, the first output of the selector of the duration of each connection processing channel not with the first input of the counter, the first outputs of which are connected to the first inputs of the reversible counter, the first output of the reversible counter through the decoder zero is connected to the first input of the first element; And, the second output is with the first input of the second element AND and the corresponding input of the first element OR the output of the pulse generator is connected to the second inputs of the reversible counter and the first element AND the first processing channel, the output of the first AND element of each previous processing channel is connected to the second inputs of the reverse counter and the first element AND of each subsequent processing channel, the second outputs of the selectors for the duration of all processing channels are connected to the corresponding inputs of the second OR element, the output of which through Consequently, the divider is divided into two and the first counter with the first inputs of the first memory register, the output of which is connected to the first input of the comparison element, the output of the comparison element is connected to the second input of the first memory register, the first input of the second counter and the second inputs of the second elements And all processing channels The outputs of which are connected to the corresponding first inputs of the decoder, the second inputs of which are connected to the outputs of the second memory register, the output of the first element OR is connected to the second input of the second account The output of which is connected to the second input of the comparison element, the inputs of the selectors for the duration of all processing channels are combined and connected to the first (INPUT of the median value | block, the input of the pulse generator is combined with the counter inputs of all the processing channels and connected to the second input of the median value, the output of the decoder is connected to the output of the median value determination unit. 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