SU968802A1 - Device for forming position characteristics of non-position code - Google Patents

Description

The invention relates to computing and can be used in high-speed digital computing devices operating in non-positioning number systems for performing non-modular operations.

A device for generating positional features of a non-positional-EO code is known, comprising an input register, a constant storage unit, a binary adder, a block of serially connected binary adders, an output binary adder, a rank adder, an output register, a transfer circuit connected by corresponding links 1,

The disadvantage of the device is low speed.

The closest technical solution to this invention is a device for generating positional features of a non-positional code, which contains a storage unit for constants for converting a code whose inputs are connected to the outputs of an input register, and the outputs are connected to the inputs of groups of adders of constants, and outputs of constants of both groups are connected to inputs adder rank

the number, the output of which is connected to the input of the register of the source rank, the output of cyj iMaTopa senior bits of the second group of adders of constants

.5 connected to the output register input, the shift register, intermediate result register connected to the output register output, correction adder, high-order transfer generation unit from the high bits to the high-order content analysis circuit, and the input blocks of the shift constants, whose inputs are connected with the outputs of the input register, and the outputs 15 are with the inputs of the shift register, and the analyzer of the sum of the higher bits, whose input is connected to the output of the summator of the older bits of the second group of adders of constants, the moves of the shift register connected to the corresponding inputs of the input register; the outputs of the registers of the source rank and intermediate result are connected to the inputs of the correction adder; the inputs of the transfer generation block from the higher bits are connected to the outputs of the correction adder and the intermediate result register, the outputs of the correction adder and the block

30 transfer generations from the high order bits are connected to the inputs of the output register and the circuit for analyzing the contents of the high bits 2.

The disadvantage of the device is low speed.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that the device for generating the positional characteristics of a no-action code containing an input register consisting of (n + 1) sub-registers on the basis of the residual classes system (SOC), whose inputs are device inputs, a group of. (p-2) blocks for storing conversion constants of non-positional code into intermediate by positional, a group of (p-2) adders modulo Rk (k - 2,3 ..., p), the register of the character and register of the sign whose outputs are respectively, the output of the correction of the sign and the output of the device. The outputs of the i-th sub-registers (i 1,2,.,., p-2) of the input register are connected to the inputs of the i-th blocks — the storage group for converting nonpositional code to intermediate positional constants / - contains a group of (p-1) comparison circuits with a constant, a group of (p-2) elements AND, element OR, output Which one is connected to the input of the sign correction register and to the first input of the sign register, and the inputs are connected to the outputs of the corresponding AND elements of the group, the first input of the first AND element is connected to the output of the first comparison circuit with the group constant, and the jth input (J. 2 , 3, ..., p-2) is connected to the first, output of the j-th comparison circuit with a group constant, the first and second inputs of the J-th element AND group are connected respectively to the second and third output of the j-th comparison circuit with a group constant , i-th input (e 3,4, ..., p-J) of the P-th element of the AND group is connected to the first Exit (-fj-2) -pa circuit comparing with konstantgry group carry output i-ro. adder modulo Rk is connected to the first input of the i-th comparison circuit with a group constant modular output j-ro of the adder modulo Rc is connected to the second input of the r-th (.g 1,2, ..., p-3) comparison circuit The second input (n-2) of the comparison circuit with a group constant is connected to the output of the n-th sub-register of the input register, the input (n-1) of the comparison circuit with the group constant is connected to the output (n + 1) - first subregister of the input .register, the first output of the (a-D) -th comparison circuit with the group constant is connected to the second input of the sign register, and the second output is are the signal output unit, i-th

the output of the first block of the storage group of the conversion constants, non-positioned code into the intermediate position code is connected to the first input of the i-ro adder modulo the Pk group,

The i-th output of the j-th storage block of conversion constants of a non-positional code into an intermediate positional (j 2,3, ..., p-2, i 1,2, ..., nj) is connected to the j-th input (i + J-. 2) -th

adder modulo pk group, (n-1) -th input (n-2) -th adder modulo pk group connected to the output (n-l) -ro of the sub-register of the input register.

The drawing shows the block diagram of the device.

Device Contains input register 1, consisting of subregisters on the basis of SOC, group of units for storing constants 2 converting nonpositional code into intermediate positional, group of adders modulo Rk 3, group of comparison circuits with constant 4, group of elements AND 5, element OR 6, register amendment mark 7, register mark 8.

The converter of the i-th digit of the non-position code 2, - (i 1,2, ..., p-2) is a circuit made on the basis of a constant

P.J- word storage by

p-1

eocf2Pj i

:

P - 1

III if i: 1

binary bits each, where through Ox C denotes the smallest integer

0 number is not less than X.

Comparison Schemes 4 are carried out. check - fulfillment of a certain condition on the input values and produce a number of signs, namely: if

c by PIJ and designate the values arriving respectively at the first and second inputs of the 4k circuit (, 2 /.., p-2) then circuit 4 at its only output employs symptom 82 according to the rule

1 if P, pj

(one)

Sa.

p (M,

.0, if Пг +5 РЬ and the scheme .4к (к 2,3, ..., п-2) on the first, second and third of its outputs produces the signs Hj, SK and n, respectively, where.

Vo, if P, P ,, - l

(2)

i if P PK.I (

1, if P.,

PI PI

K-f1

(3)

0-, if Pk + pT PK + I- Hj is the negation of the magnitude of N. The circuit 4 for input velichine 1 produces signs 1 if O. ,, if q f I, n, if .0, if I Д where Р, is an additional basis of this POSITION-MODULAR C, CALCULATION TEST. vnon eTBonLmP. vc.nopMK ,, number, satisfying the condition; RP + 7/2 q + 1; q is a fixed natural number. The device works as follows. We introduce the notation: - .Р; P, a system of pairs of mutually simple bases of the used nuclear modular number system, moreover. Р ,, 7, 2 q + 1, where q. Is a fixed natural number -IXI - the smallest non-negative deduction, comparable to X modulo P; - the whole part of a. real number x; .r VPi i.rKxtP. -i is a digit of the normalized modular code of the number | A1P (K) in the system. with modules, P2, ..., P | c (i, ..., k; k 0) ... Let it be required to determine the sign of the number Aef-q, PCn), c), P (.n), represented by in the sod-modular number system with bases P., Pj ,. .., Pn + i. / As well as the amendment of the sign r (1А1Р (п)) of the number | АГР (.. The number А in the considered number system is represented as L (, п-1 2, пИ-п-1, Пг15А - YL) - the remainder of the division of the kernel t A, the number I A | P (n) by P, defined by - formula 5 (1). L. У .- / p А -JV 117 Р, aZ ;; - | h; n ... where the quantity called the nuclear interval index of the number A is chosen so that —5 p „„., s, „.,. - o; P) c) It is known that the correction of the sign of the number IA is defined as integer r (1А | Р (п)), satisfying equality, ..., с,. „., (/ А | Р %% Then from (6) and (7) we have (5 |, 4m; ( ) From here, and also from the fact that „fClAI P (nj) takes oh two zakacheg O or 1, it follows: if n 7 2, t, „-, ,, TSG) l n °“ O follows A, O, and from 1, -1 follows A 0; if it is 2, then signs of numbers A and T Govpap give ... 1. To determine the sign of a number ... Ao -q, P (n), (n) it is enough:. 1) For all k (k 2,3, ...., p-1) to calculate indices G; Gchisla A, provided that -1 2) Sfor, irovat signs SK (to 2,3, ...; p) and Hk. (, 4, ...) according to the rules: 1, if, o, o, if id o, 1, if, o, if (, 4, ..., p) o, if -1 (k) h 1 if 1 d -1 3) Find the natural number (A) (2 it (A) n) such that for all k e (A) H ,, a He (g) O or e (A). 2 and then S 8p (d), where S is the sign of the number A, defined as 1, if A o, O, if A 0. In order to obtain a calculation formula for item 1, we put in formula (6) n to -f 1 and convert it as follows / | :: ri -... to-. .PK .. -.kr. (.. B. L-... (5. (pG-; k.,) - k) d .p () (liiil:,., - “ibK-t P ll7Tl P-II l, k1 p , / p (KHLp Vp) b -p7-jj RK YaL K4- | j KJ, that is, we get .. p ,,.,., -. Г- -Ч К-РГ-рк..М fe№ b "-It & comparing (6) and (11), we conclude - (К + -1) Р д - Рк + 1. - 11 к -г л 11. To calculate the correction. Sign T ((п)) it is enough to know that if the nth base of the modular number system satisfies the inequality Р „7, п-2, then the sign amendment tdtl RSp where A is an arbitrary integer coincides with the sign (e of the number 8.E: P ,,., -d ,,.,. p (r. (n), (, 5) defined as.. Г1, if В / О, 1о, if В О. From the above algorithms for determining the sign of the number you can see that the correction (( And P. ( .ni} can be formed as a result of the execution. pp. 1-3 of 1.; for this it suffices to note that e seo (A), where is a natural number such that for all K {Eo (L) K p) n, 1 , and HP (, (/ 0 and Еo ().. It is easy to verify that to form d S BOC, you can use the following zero expression. 5 5 "; ..,. n., 45".,. n.; .. H „., - .. + .Н4 ... H„ n | -V3H4- “ni where n, -.negative H, 4 ,. .., n- Consider the first, how the sign of the number A is determined in the device. Code fct oi. 1 ° 1, ..., n-1 A / of the number A is fed to the register, 1, Then the ia digit (i 1,2,...,. N-2) is fed to the input of block 2, as a result of which nocf about this .pam By the address oli, ri-i is read the set of values L, Pr, G °. P-1-Pp-L 1 J in the case of i T and the set of values ° li ,, m-Pu. | PiJ- -. h, n-VViPi with 1 i p - 1, j-components (j 1,2, ..., if i 1 and j 1,2,.,,, ni, if i / 2) the read set of a quadrant. The jth output of block 2 i is transmitted to the 1st input of the adder Bj. , In the same tact of operation, the device index 1 of the number A with / output of the sub-register lf, + - i is supplied to the comparison circuit 4-n-1, which, in accordance with formulas (4) and, (5), forms in its first the output sign Sn, transmitted through the second input to the sign register 8, and at the second output, which is the output of the device, sign n. If Hn: 1, then the operation of determining the sign of the number is completed - the required sign is formed in register 8 ;. if nr. 1, the process of forming the sign of the number A continues. During the subsequent log2 (n − l) cycles of device operation, block 3 performs summation of deductions applied to their inputs. The final stage of the procedure for determining the sign of the number A is carried out by comparison schemes 4, which are formed in accordance with the forms. (1-3) signs of SK (to 1,2, ..., p-2), Hk and Hie (to 2,3, ..., p-2), elements-AND 5 and OR 6 that implement the expression 16. Formed at the output of the element OR 6, the amendment t {| A | P (p)), which in this case coincides with the sign of the number A, is transmitted to register 7 and through the first entry into register 8. This completes the operation. Thus, introducing into the device a group of comparison circuits with a constant, a group of AND elements, an OR element and the corresponding connections allows the device to increase its speed to 2 + 1OD (n-1) modular operations, which is higher than that of the known, more than twice. Formula of the invention A device for generating positional characteristics of a non-position code comprising an input register consisting of (n + 1) sub-registers based on a residual class system (JUICE) whose inputs are device inputs, a group of (n-2) storage units Constants of conversion of a non-posed code to an intermediate positional, group of (p-2) adders modulo Рк (to 2,3, ..., p), sign correction register and sign register, the outputs of which are respectively the sign correction output and the sign output devices, i- outputs subregister x (i 1,2,..., n-2) input register

Claims (5)

Claim A device for generating positional characteristics of a non-positional code containing an input register consisting of (n + 1) sub-registers on the bases of a system of residual classes (RNS), the inputs of which are device inputs, a group of (n- 2) storage units for the constants of conversion of a non-positional code into an intermediate positional one, a group of (n-2) adders modulo Pk (k = 60 = 2, 3, ..., p), the sign correction register and the sign register, the outputs of which are respectively the sign correction output and the device sign output, outputs of the i-th sub-registers 65 (i = 1,2, ..., η — 2) input register 1 ij are connected to the inputs of the i-th blocks of the storage group of constants for converting a non-positional code into an intermediate positional code, characterized in that, in order to improve performance, it contains a group of (n-1) comparison schemes with a constant, a group of (n-2 ) AND elements, an OR element whose output is connected to. the course at the sign correction register and to the first input of the sign register, and the inputs are connected to the outputs of the corresponding AND elements of the group, the first input of the first AND element is connected to the output of the first circuit with the group constant, and the jth input (j = 2,3 , ..., η — 2) is connected to the first output of the j-th comparison circuit with a group constant, the first and second inputs of the j-ro element And groups are connected respectively to the second and third output of the j-th comparison circuit with a group constant; . Eth input (E = 3, 4, ..., nj) of the? Element of the And group is connected to the first output of the (? +] -2) th comparison circuit with the group constant, the transfer output of the i-ro adder modulo Pk is connected to the first input of the i-th circuit comparison with the group constant, the modular output of the j-th adder modulo Pk is connected to the second input of the r-th (r = 1,2, ..., n-3) circuit of comparison with the group constant, the second input (n-2) -th comparison circuit with a group constant is connected to the output of the η-th sub-register of the input register, the input of the (n ~ 1) -th comparison circuit 5 with a group constant connected to the output of the (n + 1) -th sub-register of the input register, the first output of the (n-1) -th comparison circuit with the group constant is connected to the second input of the 10-character register, and the second output is the signal output of the device, i 15th output of the first block of the storage group for converting constants of a non-positional code into an intermediate positional code 15 is connected to the first input of the i-ro adder modulo the Pk group, i -th output of j-ro block storage of constants for converting a non-positional code into an intermediate positional code (j = 2 , 3, ..., n-2, 1 = 1,2, ..., n — j) by is connected to the j-th input of the (i + j - 2) -th adder modulo Pk group, (n-1) -th input of the (n-2) -th adder modulo Pk group of connect to the output (nl) -ro of the subregister input register.