SU960957A1 - Analogue storage - Google Patents

Description

(54) ANALOG STORAGE DEVICE

The invention relates to computing and can be used to study one-time processes in radar, radio operators. Wick, television, nuclear physics, as a remote instrument to the oscilloscope for studying one-off processes on its screen.

For recording and subsequent multiple reading of single signals, memory devices using movable magnetic storage media (tapes, drums, discs), as well as electron beam tubes with a visible image, are known.

However, the secret of the device is characterized by constructive complexity, low reliability and high cost.

Also known are storage devices with stationary magnetic anshand memory elements, such as transfluxors, in which they are manufactured; time signature quantization, memorization of process values corresponding to quantization moments in separate elements. tl memory

However, pulsed negative communication is used to write information to the memory elements, and the memory elements are overloaded in the presence of switching elements in the writing circuit and in the signal reading circuit when reading, which reduces the speed and accuracy of the device. .

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Closest to the invention by technical essence is an analog device for storing one-time signals, containing a collecting element covered by a feedback loop, made in the same time as the delay element, the source of the reference voltage, connected to the first input of the reference element, k. In addition, the device contains one-shot, peak detector. The reference voltage source is made in the form of a sawtooth voltage generator, with which the information signal is compared to the given time interval at the moment

25 of their equality, the one-shot forms a rectangular pulse written to the cumulative element — the delay element. Gradually, pulses of equal duration at different distances from one another are recorded in the delay element. These distances carry information about the amplitude of the quanta of a single process 12. The disadvantages of the known device are the limited amplitude dynamic range of the memorized signal and the limited number of choices (number of time slices) determining the accuracy of the memory. The principle of operation of the device is to transform the amplitude of the memorized signal during the time between pulses produced by a single vibrator. Therefore, the memory volume of the cumulative element should be equal to the product of the number of samples and the number of gradations in amplitude. The use of a delay element in the known storage device, which contains the recording current generator, the read amplifier, the square pulse shaper, does not allow a significant increase in the memory capacity, due to the large amount of equipment required, large dimensions, and power consumption. In this device, the amplitude dynamic range is inversely proportional to the number of quantizations of the signal over time, since an increase in the amplitude of the storage signal leads to an increase in the processing time of one quantization, which leads to a reduction in the number of quantizations. In addition, in the device at high speeds of increasing the saw-tooth voltage, the moment of its comparison with the memorized signal has a large scatter, which leads to a decrease in the accuracy of memorization. Thus, the known devices cannot ensure the storage of single signals with a large amplitude dynamic range with high accuracy and for a long time. Large possibilities in this direction are opened by devices with charge-coupled communication (CCD). CCDs provide accurate, clock-controlled control signal delay, which can vary from hundreds of seconds to several seconds. They are compact, consume little power, which allows for high volume delay lines. The disadvantage of a CCD is the limited storage time of analog information, due to smoothing with time the stored information caused by the accumulation of additional carriers in the bulk of the semiconductor and at the silicon-silicon dioxide interface. So that the storage time of information in a CCD is not limited to the time of heat relaxation of potential meters, the information must be periodically regenerated. It is easy to do this if 1 | nform atsi is represented in digital form. When recirculating purely analog information, very strict requirements are imposed on stability, linearity and other characteristics. Therefore, the use of a CCD in a known device without changing its functional scheme is not brought to the desired result. The aim of the invention is to improve the accuracy of the device and the expansion of its amplitude dynamic range. The goal is achieved by the fact that in an analog storage device containing a main storage element, a clock pulse generator, the first output of which is connected to the input of the phase voltage generator, the output of which is connected to the first input of the main storage element, the source of the reference voltage, the output of which is connected to the first input of the comparison unit, the keys, the control unit, the first and second inputs of which are connected to the control and reset buses ,. the additional accumulative element, element I, counters, adder and amplifier are introduced, the first input of which is connected to the output of the main storage element and the first input of the first key, the second input of the first key is connected to the output of the first element And, the output of the first key is connected to the input of additional memory element whose output is connected to the second input of the comparison unit, the output of the comparison unit is connected to the second input of the amplifier, the output of which is connected to the first input of the second switch, the output of the reference source voltage is connected to the first input of the third key, the first input of the fourth key is the input of the device, the outputs of the second, third and fourth keys are connected to the inputs of the module, the output of which is connected to the second input of the main storage element and the output of the device, the output of the first counter is connected to the third input of the control unit, the first and second inputs of the first element I are connected respectively to the first output of the second counter and to the first output of the control unit, the second and third outputs of which are connected respectively, with the first inputs of the second and third elements And, the second input of the second element And is connected to the first output of the second counter, the second inlet of which is connected to the second input of the third element And, the output

which is connected to the second input of the fourth key and to the first input of the first counter, the second input of the first counter is connected to the second output of the control unit, the fourth output of which is connected to the second input of the second key, the third input of the third element And is connected to the second output of the clock generator and to the first the input of the second counter, the second input of which is connected to the first output of the control unit, the output of the second element I is connected to the second input of the third key.

The essence of the invention is that an analog signal is converted into a set of m discrete samples, each 1, (n + 1), (2n + 1) discrete sample n 1 - t, n -S-,

where K is an integer, is replaced by a different sample of reference Voltage. The resulting sequence is memorized using a CCD, when a CCD sequence is read, a sample of the reference voltage is selected, compared to the voltage of the source of the reference voltage, and the degree of degradation of the sample of the reference voltage produces an effect on the entire sequence of samples that follows the reference, compensating for the degradation .

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - time diagrams of his work.

 The device contains a cumulative element 1, made on a device with a charge connection, a generator of 2 clock pulses, a shaper 3. phase voltages, a source 4 of the reference voltage, unit 5 of comparison, keys 6–9, additional accumulative electric element 10 , executed, for example, in the VI: de condenser memory cell, elements 11-11, control block14, counters 15 and 16, adder 17, control bus 18, reset bus -19, amplifier 20 with adjustable gain. Comparison unit 5 may be configured as a differential amplifier.

The device works as follows.

Before the pulse arrives on bus 18, keys 7 and 9 are closed, and key 8 passes the reference voltage from source 4 to the input of adder 17 only for every 1, (n + 1),. (2n + 1m), etc. clock pulse, at the output of the adder 17 there are samples of the reference signal with a duration equal to the duration of the clock signal, the number of which corresponds to 1,. (n + 1), (2n + 1) and. generator pulses 2 clock frequency. Sample reference

the voltages are fed to the input of element 1 and to the output of the device. Each of the samples of the reference voltage appears at the output of the CCD element at a time equal to tT, where m is the number of transfer cycles of the device with the charge coupling, T is the period of the clock pulses. And the number n is chosen

so that K, where K is an integer,

and the PT time would not exceed the storage time of the additional storage element 10 for a given accuracy. Under this condition, the sampling time of the reference voltage at the input and output of element 1 will be the same. The samples of the reference voltage, the passage through the CCD, are delayed by a time equal to n "T, and degraded in amplitude. With a CCD output, each sample, for example, the first through key 6, goes to an additional cumulative element 10 until the next sample of the reference voltage arrives. Comparison unit 5 compares the voltage from the reference voltage source 4 with the value of the sampling voltage of the reference signal from element 10 and produces the gain control voltage of the amplifier 20. The gain of the amplifier 20 is set so that the voltage of the reference sample at its output coincided with the level of the reference voltage, and is refined after each subsequent sample of the reference voltage from the output of the CCD 1 arrives at its input.

Timing diagrams illustrate the operation of the device. Provided that

is permissive.

level

and the level O - prohibiting the passage of a signal through the elements. And, the keys. Timing diagrams are presented for case.

After the arrival of the starting pulse at the outputs of block 14, which is a logical block made on the triggers, the elements of NAND, signals are generated, as shown in diagrams 14a, 14b, 14d. The signal 14b is allowing for the passage of clock pulses to the counter 15, the signal 14a is prohibiting the passage of pulses to the input of the key 6. By the leading edge of the inhibitory signal 14a the counter 16 is set to zero, the counter 16 generates the resolution signals of the diagram 16a to pass to the adder 17 Reference Voltage and Inhibit Signal - Chart 166 for passing the signal under study while the reference signal is present at the input of the adder 17. The counter 16 generates the output pulses on 1, (n + 1), (2n + 1) clock pulses that came on him after the starting pulse. Output element

13, and forglirovanii sequence of clock pulses, in which 1 (p. + 1), {2n + 1G pulses are missing. This sequence enters the control input of the key 9 and the counter

15; Key 9 quantizes the memorized analog signal over time, i.e. converting it into a sequence of pulses, the amplitude of which corresponds to the instantaneous amplitude values of the analog signal at the time points corresponding to the presence of a signal at the control input of the key 9. Counter 15 has a conversion factor (m-T). Each pulse, multiple (m-K) at the input of the counter 15p, produces at its output a signal that sets the control unit .14 to the initial position, At the second and fourth outputs and the block

14, at this moment, a prohibiting level appears for passing through the switch 8 of the reference voltage and allowing the pass level through the switch b of the output signal of the amplifier 20 with an adjustable gain factor. Counter 15 operates exactly as long as it is needed for any sampling through the CCD 1 from its output to output (tT). The signal at the first output of control block 14 (diagram 14a) permits the passage of reference voltage samples passed through

The CCD 1 to the element 10, and in each period the gain of the amplifier 20 is adjusted. Since the key 7 is opened by the signal from the fourth output of the control unit 14 (diagram 14d), and the keys 8 and 9 are closed, then the input of the CCD 1, and therefore and the output of the device receives samples of the analog signal, delayed by the time tT. After a time t-T, the sampling of the analog signal reappears at the output, etc. circulate to those times until the Reset signal is sent to bus 19, which sets the device to its original state and interrupts the feedback loop.

After the arrival of the Reset pulse, although the signals from the previous sample will still be present at the output of the CCD 1, the device is already ready to store the next sample of the analog signal arriving at the input.

The reset signal in the device can be generated automatically by counting the pulses coming from counter 16 after the arrival of the starting pulse and comparing the code of the additional counter 16 with a predetermined code.

Thus, in the proposed device, the analog signal is stored indefinitely as long as the feedback circuit is closed. The information is regenerated by the degradation stage, the sampling stage. a reference voltage corresponding to 1, (n + 1), (2n-t-l) pulse number of the clock signal.

The algorithm of the proposed device does not provide for any amplitude conversion, as is the case in the known device, in which the amplitude of the storage signal is converted in time. Therefore, the volume of the memory of the memory element in the proposed device is determined by the number of quantizations of the storage signal over time.

In the known device, the memory volume of the cumulative element is determined by the product of the number of quantizations in time and the number of gradations in amplitude. Therefore, in the proposed device, the amplitude dynamic range of the signal is not limited by the memory size, but is determined by the possibilities of the CCD and can be 100.

In addition, it allows one to increase the number of quantizations with respect to time, a defined task, the accuracy of memorization, by a number of times equal in the known device to the number of gradations of the memorized signal in amplitude. If in the known device the number of gradations in amplitude is 10, then in the proposed device the number of quantizations determining the accuracy of memorization increases 10 times.

The advantages of the accumulative element used are a large amount of memory, capacity, low power consumption, accurate, manageable delay.

The use of the proposed device is most effective where a large number of signal quantizations are required over time, in particular when recording the electrical analogue of a video image (television frame

For example, 1, at. The number of decomposition of a television frame into () discrete elements and with the number of gradations in amplitude (brightness) equal to 32, it is necessary to have a memory capacity of a storage element in a known (-32) cell, which is an expensive and complex device.

The proposed device is designed specifically for a CCD, which makes it possible to realize, for example, () cells in a single chip.

Claims (2)

Invention Formula An analog storage device containing a main storage element, a clock pulse generator, the first output is connected to the input of the phase voltage generator, the output of which is connected to the first input of the main storage element, a source of reference voltage, the output of which is connected to the first input of the voltage comparison, the keys, the control unit / first and second inputs of which are connected to the control and reset buses, are different in order to increase the accuracy of the device and expand its amplitude dynamic range, an additional cumulative element, elements I, counters, an adder and an amplifier, the first input of which is connected to the output of the main cumulative element and the first input of the first key, are entered, the second input of the first key is connected to the output of the first element And, the output of the first key is connected with the input of the additional storage element, the output of which is connected to the second input of the comparison unit, the output of the comparison unit is connected to the second Bx of the amplifier, the output of which is connected to the first input of the second the first key, the output of the reference voltage source is connected to the first input of the third key, the first input of the fourth key is the device input, the outputs of the second, third and fourth keys are connected to the inputs of the adder, the output of which is connected to the second input of the main storage element and the output of the device, the output of the first counter is connected to the third input of the control unit, the first and second inputs of the first element I are connected respectively to the first output of the second counter and to the first output of the control unit, second oh and the third outputs of which are connected respectively to the first inputs of the second and third elements And the second input of the second element And connected to the first output of the second counter, the second output of which is connected to the second input of the third element And, the output of which is connected to the second input of the fourth key and the first the input of the first counter, the second input of the first counter is connected to the second output of the control unit, the fourth output of which is connected to the second input of the second key, the third input of the third element I is connected to the second output home clock generator and with the first input of the second counter, the second input of which is. It is connected to the first output of the control unit, the output of the second element I is connected to the second input of the third key. Sources of information taken into account in the examination 1.Avtorskoy certificate of the USSR 360695 cl. G 11 C 27/00, 1971. 2. Abyurskoy certificate of the USSR № 769634, cl. 6 PS 27/00, 1978 (prototype).