SU1124326A1 - Digital spectrum analyser in orthogonal base - Google Patents

Abstract

DIGITAL ANALYZER OF THE SPECTRUM IN THE ORTHOGONAL BASIS, the contents of the first and second multipliers, the first whose inputs are connected to the information output of the analog-digital converter, the information input of which is the information input of the analyzer, the first and second totalizers, the clock pulse generator, the output of which is connected to the clock input A / D converter, first and second registers and counting counter input, characterized in that, in order to improve speed, a group of elements is introduced into it ntov And, the group of elements is NOT, the third register, the third adder, the third multiplier, the element OR-NOT, the one-shot and the block of permanent memory, the information output of which is connected to the first input of the third multiplier, whose closure is the information output of the analyzer, the output of the first the multiplier is connected to the first input of the first adder, the output of which is connected to the information input of the first register, the output of the i-ro (, I) whose bit is connected to the first input of the i-ro element AND group, the output of which is connected to the -th input of the first g the second adder, the output of which is connected to the second input of the third multiplier, the information output of the second register is connected to the second input of the second multiplier, the first input of the third adder and the information input of the third register, whose information output is connected to the second input of the third adder whose output is connected to the second input of the first the multiplier and the information input of the second register, the installation input of which is connected to the installation input of the third register and connected to the output of a single RATOR, whose input is connected to the transfer input of the third adder, the second inputs of the AND elements of the group and connected to the output of the element OR NOT, the i-th input of which is connected to the input of the i-th bit of the address of the block of memory and connected to the output of i- ro bit counter, the output of the clock generator is connected to the clock input of the third register, the output of the i-bit of the second multiplier is connected to the input of the i-fo element of the NOT group, the output of which is connected to the i-th input of the second group of the second adder, the transfer input of which is the entrance back no logic analyzer unit.

Description

The invention relates to computing and can be used in real-time digital signal processing systems. A spectrum analyzer in Walsh and Haar bases is known, which contains an ADC receiving register, a digital integrator, a group of shift registers and a control unit. Such devices allow 1 to calculate the spectra of signals in the Walsh and Haar bases of the dimension, require at least one addition to calculate one conversion coefficient, and introduce a delay between the input of samples of the converted signal and input the corresponding coefficients of at least N clock cycles l. The disadvantages of such devices are the poor set of dimensions of the signal to be converted (2 samples), poor convergence of the Walsh and Haar coefficients when representing signals of the type of real exponentials, and a large delay in calculating orthogonal transformations, which limits the use of these devices in real-time systems closest to the proposed The technical entity is a digital Fourier transform generator containing an analog-digital converter, the input of which is connected to the input of the device, and the output to the input of multipliers, clock generator, frequency divider, counter, input of which is connected to the output of clock generator, argument code generator, code converters, multipliers, adder shift registers and coincidence circuits 2. Such a device allows calculating the value of the Fourier spectral coefficients of a discrete signal and is characterized by low speed (a single spectral coefficient is formed during the N cycles of operation of the device), as well as narrow functionality associated with the poor convergence of the Fourier series when representing signals of the form to ljii) - I.Aj6 ,, .. The purpose of the invention is to increase the speed of the digital spectrum analyzer in an orthogonal basis. 262 The goal is achieved by the fact that a digital spectrum analyzer in an orthogonal basis, containing the first and second multipliers, the first inputs of which are connected to the information output of the analog-digital converter, the information input of which is the information input of the analyzer, the first and second adders, a clock generator , the output of which is connected to the clock inputs of the analog-to-digital converter, the first and second registers and the counting input of the counter, a group of elements I is entered, a group of elements in NOT, a third register, a third adder, a third multiplier, an IL-NOT element, a one-shot and a fixed memory unit whose information output is connected to the first input of the third multiplier, the output of which is an information output of the analyzer, the output of the first multiplier is connected to the first input the first adder, the output of which is connected to the first input of the first register, the output of the i -th ((1,1) bit of which is connected to the first input of the i-ro element AND group, the output of which is connected to the -th input of the first group of the second adder, you one of which is connected to the second input of the third multiplier, the information output of the second register is connected to the second input of the second multiplier, the first input of the third adder and the information input of the third register, whose information output is connected to the second input of the third adder, the output of which is connected to the second input of the first multiplier and Information the input of the second register, the installation input of which is connected to the installation input of the third register and connected to the output of the one-shot, the input of which is connected with the transfer input of the third adder, the second inputs of the AND elements of the group and the CONNECTION-To the output of the S1I-NO element, the i-th input of which is connected to the input of the i-th bit of the address of the permanent memory unit and connected to the output of the counter bit The output of the clock generator is connected to the clock input of the third register, the output of the i-ro bit of the second multiplier is connected to the input of the i-ro element of the NOT group, the output of which 31 is connected to the i-th input of the second group of the second adder whose transfer input is the input of the task of the analyzer logic unit pa. The introduction of additional equipment into the device allows calculating the spectral transformation coefficients of a signal using a system of orthogonal basis functions based on Fibonacci numbers, which provide an optimal approximation of a wide class of signals such as real exponentials and their sums obtained by solving differential equations with real roots of characteristics. of equations. At the same time, this device provides the i-ro calculation of the spectral coefficient with a delay of one cycle relative to the i.-ro signal reference. Fig, 1 shows a block diagram of a digital spectrum analyzer in an orthogonal basis; in fig. 2 timing charts of the device. The device contains an analog-to-digital converter (ADC) 1, the first and second 3 multipliers, the first adder 4, the first register 5, the group of elements 6, the second adder 7, the group of elements 8, the second 9 and the third 10 registers, the third adder 11 , clock generator 12, counter 13, element OR-NOT 1A, constant memory unit 15, one-shot 16, third multiplier 17. FIG. 2 diagram a characterizes the pulses at the generator output; b - signals for recording information in registers 5, 9 and 10; in - the sequence of coefficients bj at the output of the multiplier 17; g, d, e are the signals at the outputs of the bits of the counter 13; for g is the signal at the terminal of the element IPI-HE 14; and - one-shot pulses 16. This device allows calculating the spectral coefficients of a discrete signal in accordance with the formula b..aj.; U), (1) N is the transform dimension (N is any natural number); 124326 5f function corresponding to fO; (where 2Q D see. And image, i.e., 55 N (1) .spec 4 bj is the i-th generalized spectral coefficient; a; - j-th sample of the signal being converted;; (J ) the value of the 1 st baseline on the i-th cycle, determined by wearing npHl jti4l (r "odNl,)) - jK; -Pj., with H), C O with ji +« (wod N) j P: - je Fibonacci number p, Pr 1 and Pi-P | -5 ri-. the normalizing coefficient W with i N l arbitrary f (j), f) (j) compute a sum of the form 5-Zl; lj) -f, U), p .. .pp-u, p; vp - M rs 1 1 + r X Ki-d pr4 - tfilp ipJnpn..K, (3) it is known that .ZP P - P {,. Thus, from expression (3) follows from r, -х Г О РИ, S SLiUiVi). f, j-1 LI with ic. J, the set of functions f, (. 1) N calls an orthonormal system on the periobasic system, and the expression1 {e allows us to find the coefficients of the lateral transformation of the signal ai using the system of orthogonal functions. The inverse transform is equivalent to the direct, i.e., equivalent to the direct, Oj-X L-1- (i). For example, with N 7, the basic functions have a VDV -1,0,0,0, O, O, 1., (.-UO, 0,0,0,1 ...); (Y.2, -2,0,0,0,1 .1.2,3, -3,0,0,1 (1,1,2,3,5, -5,0,1 ...); (1,1,2,3,5,8, -8, U ..)} (, 3,5.8,} 2,.,.); Substituting expression (2) into expression (1) we get b, “( , avP, -c 2PiV i biKaVpA + 0 (2pa-a, Pi) -V2, V (i р; 1-1 ;, (4) Pe) -a c1е-re) «H Type of expression (4) allows It is necessary to obtain spectral conversion coefficients of the signal using a system of orthogonal functions, which significantly reduces the required equipment and reduces the delay between the input signal of the converted signal and the output of the spectral coefficients at the output of the device. It counts modulo N pulses of the generator 12 and periodically sets to zero, while registers 9 and 10 are also set to zero by a one-shot 16, triggered by a voltage differential, the output of the element OR-NOT 14 (Fig. 2, g, i) and thus the device is in its initial state.The logical unit from the output of the OR-NOT 14 element enters the transfer input of the adder 11 and the second input of the group of elements 6, ADC 1 from the generator output 12, registers 5, 9, and 10 and meter 13 modulo I receive an impulse 26 sy. The information input of the second register 9 receives the code C from the output of the adder 11, determined by the sum of the codes of the registers 9 and to and the transfer signal Q from the output of the element OR NOT 14 to the information input of the third register 10 and the code from the output of the second register 9. Thus, with the arrival of the -th clock pulse at the clock inputs of the registers 9 and 10, the code 10 is written into the register 10; the code P.-, + P, +2 is written into register 9, where the code recorded in register 9 is in the iM cycle. Since at the output of the IPI-NOT 14 element there is a logical unit level only at the zero state of the counter, then G 1 at (1 O at i 1. Thus, at the output of the adder 11, a sequence of Fibonacci numbers 1,1,2,3,5 , 8, ..., P - ,, PV ,, Р Р {-, + Р, -n. (5) At the output of register 9, the definable expression P. is formed — p. J,., With it 1, - 1o with i 1 (6) An analogue signal is fed to the input of the ADC 1. At the output of the ADC 1, codes a, which are numerically equal to the values of counts, are formed at the frequency determined by the clock frequency of the generator signal. These codes arrive at the first dvars of multipliers 2 and 3, to the second inputs of which, in the iM cycle, receive the codes P, P-, defined by expressions (5) and (6), respectively. At the output of multiplier 2, a sequence of codes C is generated, that arrive at the input of the adder 4. In the first cycle of operation of the device, the logical unit from the output of the element OR NOT 14 arrives at the corresponding inputs of the elements of AND 6 group. . . Thus, in the first clock cycle: the elements of the AND 6 group are closed by the level of the logical unit from the output of the OR-NOT 14 element, and at its output a zero code is created, which is input to the adder 4. Thus, in the second clock, register 5 is written code C, from the output of the summer 4. In subsequent cycles, the second input of the adder 4 through the open elements And 6 receives a signal from the output of the register 5. Thus, the accumulator 4 and the register 5 form an accumulating adder, the output of which (register output 5) in the i-th cycle, the code R is formed; K.-PK-I (7). This one arrives at the input of the adder 7. At the other input of the adder 7, the NOT 8 code receives the code from the smart code 3 code, and the logical unit level is continuously applied to the transfer input of the adder 7. Inverting each of the code bits from the output of smartly resident 3 in combination with adding one to the lower bit is equivalent to changing the sign of the code sz | R- . Adder 7 performs the summation in the additional code of numbers, and at its output, in the so-called code. In accordance with expression (6) (7) Eaepe-arP,., I-t / li-i7 (8) where. : Code from the output of the counter 13 step. em on the address inputs of block 15, in ko. The torus at the i-th address is the numerical value of the coefficient K., GTRI iUofcc (ipecaj i-i) at 1 (coA lARES 00 ... o) 1RmRmn At the input of the multiplier 17 receives the code / 5; from the output of the adder 7, the multiplier 17 performs the operation of multiplying the codes K, - ,, and, therefore, from its output in accordance with the expression (8), in the i-th cycle, the orthogonal transform coefficient b is removed, -. The generator 12 forms rectangular pulses with a duty cycle of 2 (FIG. 2a), the leading edge of each pulse are written, the codes in registers 5, 9 and 10 and the reading of the code from A / D converter 1 (FIG. 26), all other blocks of the proposed device are asynchronous , do not require additional clocking and. Thus, after time t., determined by the signal propagation delays in blocks 2, 3, 4, 6, 7, 8, 11, 14, 15 and 17, the code of the corresponding conversion coefficient is generated at the output of the multiplier 17 (Fig. 2c) The counter 13 performs pulse counting modulo N. FIG. 2 g-e shows the signals at the outputs of the bits of the counter 13 for the case. The Nth pulse translates counter 13 to the zero state. At the output of the element 14, the positive voltage drop (Fig. 2g), which starts the one-shot 16, is triggered. At the output of the one-shot 16, a short pulse is formed (Fig. 2i), which registers 9 and 10 to the zero state. the circuit returns to its original state, and a new orthogonal transform cycle begins. The rear edge of the pulse (Fig. 2i) at the output of the OR-NOT 14 element coincides with the beginning of a new series of spectral coefficients. Technical appraisal advantages of the proposed device consist in the fact that due to the introduction of additional equipment, the speed of the device is significantly increased and is minimal compared to the known devices of fast Fourier transforms, Walsh, Haar, the delay between the arrival at its input of the i -th sample of the converted signal and the appearance at its output of the 1st spectral coefficient. In this case, the device can be implemented for any dimension of the transform no more difficult than the fast Fourier transform device due to the fact that the basis functions are calculated using operations on integers (except multiplying by normalizing coefficients at the end of the transform). This fact also makes it possible to increase the accuracy of the conversion compared to the DFT with comparable accuracy in the representation of the input signals.

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Claims (1)

DIGITAL SPECTRA ANALYZER IN ORTHOGONAL BASIS, containing the first and second multipliers, the first, the inputs of which are connected to the information output of the analog-to-digital converter, the information input of which is the information input of the analyzer, the first and second adders, the clock generator, the output of which is connected to the clock inputs of the analog -digital converter, first and second registers and counter input of the counter, characterized in that, in order to improve performance, a group of AND elements is introduced into it, a group of elements NOT, a third register, a third adder, a third multiplier, an OR-HE element, a single vibrator and a permanent memory unit, the information output of which is connected to the first input of the third multiplier, the output of which is the information output of the analyzer, the output of the first multiplier is connected to the first input of the first the adder, the output of which is connected to the information input of the first, first register, the i-ro output (i = 1, I) of the discharge of which is connected to the first input of the i-ro of the AND element of the group, the output of which is connected to the <-th input of the first group of the secondthe adder, the output of which is connected to the second input of the third multiplier, the information output of the second register is connected to the second input of the second multiplier, the first input of the third adder and the information input of the third register, the information output of which is connected to the second input of the third adder which is connected to the second input of the first multiplier and the information the input of the second register, the installation input of which is connected to the installation input of the third register and connected g to the output of the one-shot, the input of which connected to the transfer input of the third adder, the second inputs of the AND elements of the group and connected to the output of the OR-NOT element, the i-th input of which is connected to the i-ro of the discharge address of the permanent memory block and connected to the output of the i-ro discharge of the counter, the clock generator output pulses are connected to the clock input of the third register, the output of the i-ro discharge of the second multiplier is connected to the input of the i-ro element of the NOT group, the output of which is connected to the i-th input of the second group of the second adder, the transfer input of which is the input of the logical unit analog isator.