SU960781A1 - Device for calculating microprocessor system time intervals - Google Patents

Description

The invention relates to computing and can be used. in microprocessor-based computing and control systems that operate in real time, when conducting scientific experiments and managing technological processes. A microprocessor dp timer contains a first counter with a specified conversion factor, working on subtraction and controlled by clock signals, the first counter creates a village. But one of the many possible output signals whose frequency is obtained by dividing the clock frequencies by a Predetermined number, not which is a power of two. The first counter is connected to the address bus group to select one of its outputs. A second counter, also operating in subtraction mode, is connected to the data buses to write numbers to it. The output of the first counter coe; c№i is not with the input of the second counter. When the second counter counts to zero, an interrupt signal is output to the microprocessor 111. A device for calculating time intervals is also known, comprising a counter, a control unit, the first AND element, a prohibition element, a trigger, a generator, a counter with a forced installation of a code, a group of AND-NOT elements , the second element And the signal shaper recording J. Ngdabelya; A programmable timer containing daylight transceivers, de-scrambler, control unit and counters is close to the proposed one. The disadvantages of the 1mm timer program are: the lack of possibilities for changing the clock frequency on computer commands; prohibiting the issuance of requests for interruption of the processor program; tacting of the work of the programmable timer from a remote external source, as well as the input into the computer of the state of the prohibition signals of the counters. For the timer, the measurement of the duration of the pulse signals supplied to the meter inhibit input should be carried out programmatically by polling and analyzing the contents of the counters. In this case, the polling period of the state of the counters must be greater than the period of the clock pulses at the counter input, which leads to a slower response of the computer to the change of the pulse front by a time equal to the polling period. The aim of the invention is to increase the speed of the device. This goal is achieved by the fact that the device for calculating time intervals of microprocessor systems containing a transceiver unit, a decoder, a control unit and counters, the first input-output of the transceiver unit connected to the information input-output device, the first and second inputs of the decoder are connected to The address and control inputs of the device, the read / write control outputs of the decoder are connected to the read and write enable inputs of the control unit, the outputs of which are o are connected to the control inputs of the respective counters, the second input-output of the transceiver unit is connected to the information inputs-outputs of the counters and the address input of the control unit, a frequency divider, a frequency switch, triggers and elements And by the number of counters, level normalizer, pulse switch and input register, while the control input of the device is connected to the input of the frequency divider, the output of which is connected to the information input of the frequency switch, the control input of which is connected to the second input ohm-output of the transceiver unit and the trigger setup inputs whose reset inputs are connected to the decoder reset control output, the trigger outputs are connected to the first inputs of the corresponding elements and the second inputs of which are connected to the outputs of the corresponding counters, the outputs of the And elements are connected to the information outputs of the device, the switch enable input the frequency is connected to the output of the programming of the decoder frequency, the additional information input of the device is connected to the input of the level normalizer, pack The input input register input is connected to the decoder reception control output, the first and second inputs of the pulse switch are connected to the outputs of the frequency switch and the level normalizer, respectively, the first and second outputs of the pulse switch are connected to the clock inputs and the inhibit inputs, respectively, and the first and second information the inputs-outputs of the input register are connected respectively to the second input-output of the transceiver unit and the second input of the impedance module. In addition, the level regulator contains rectifiers, filters, and optocouplers, the rectifier inputs are connected to the normalizer input, and their outputs are connected to the inputs of the corresponding filters, the inputs of optocouplers are connected to the outputs of the corresponding filters, and the outputs of optocouplers to the output of the normalizer. In this case, the control unit contains a register, write decoders, read decoders. Pulse drivers, control triggers, counting triggers, first and second OR elements and switches by the number of counters, the register input connected to the address input of the unit, and the register output connected to the read and write decoder information inputs. the control inputs of which are connected to the read and write enable inputs of the control triggers, pulse drivers and OR elements are connected to the outputs of the read decoders and connected to the inputs of the pulse drivers and installation inputs O of control triggers whose installation inputs 1 are connected to the enable inputs read and write block, the first and second outputs of the write decoders are connected to the first inputs of the first and second OR elements, respectively, the third outputs of the decoder B are connected to inputs of flip-flops and counting control input of switch, first and second inputs of which are connected respectively with unit and zero outputs countable triggers and pegylated rvye and second switch outputs are connected to second inputs respectively of first and second OR elements. Figure 1 shows the structural diagram of the device; Fig. 2 is a functional block diagram of the control unit. The device contains data transceivers 1 connected to the output of the decoder 2 and the internal bus 3 to which the meters 4 are connected, the control unit 5, the program-controlled frequency switch 6, the register 7 and the triggers 8. The transceivers 1 are connected to the information input-output 9 of the device The decoder 2 is connected to the address input-output 10 and the control input output 11 of the device. The control unit 5 is connected to the control input of each counter 4 by buses .12 and to the output of the decoder 2 by bus 13. The decoder 2 is also connected to the software controlled frequency switch 6, the register 7 and the trigger 8. The input of the frequency divider 14 is connected to the control input 15 devices. The outputs of the divider frequency 14 are connected to the inputs of the switch used b parts. One of

the input groups of the switch 16 pulses are connected by bus 17 to the outputs of the frequency / friend switch b; the group of inputs of the switch 16 is connected by buses 18 to the outputs of the normalizer 19 level, the inputs of which are connected to the additional information input 20 of the device. One of the two groups of outputs of the switch 16 is connected by bus 21 to the inputs of clock pulses of counters 4, .group of the outputs of the switch 16 is connected by bus. 22 with the prohibition inputs of the counters 4 and the inputs of the register 7. The output of each of the flip-flops 8 is connected to the first input of the corresponding element AND 23, the second input of each of the latter is connected to the output of the corresponding counter 4, and the outputs of the elements And 23 are connected to the information outputs 24 of the device.

The level normalizer contains rectifiers 25, the inputs of which are connected to the input of the normalizer, and the outputs are respectively connected to the inputs of filters 26, the outputs of which are connected respectively to the inputs of optocouplers 27, the outputs of which are the outputs of the normalizer 19 level.

The control unit (FIG. 2) contains a register 28 and a meter control circuit 29, the number of which corresponds to the number of counters 4, the register

28 has inputs connected to the decoder 2 by a line belonging to the bus 13 and to the internal bus 3, as well as two outputs connected to two of the five inputs of each of the meter control circuits 29. Each circuit 29 comprises a write decoder 30 and a read decoder 31, two pulse drivers 32 and a control trigger 33. At the same time, the enable input 34 of the write decoder 30, the enable input 35 of the read decoder 31, and the input 26 of the setup 1 of the trigger 33 are connected to the outputs of the decoder by 2 lines belonging to the bus 13. The write decoder 30 has three outputs connected to the input of the first pulse generator, the first output connected to. the first input of the OR element 37, the second with the first input of the OR element 38, and the third with the input of the counting trigger 39 and the first input of the switch 40. The counting trigger 39 has two outputs connected to the second and third inputs of the switch 40. The switch 40 has two outputs The first of which is connected to the second input of the element OR 37, and the second to the second input of the element OR 38, The outputs of the element OR 37 and the element OR 38 are the outputs of the pulse former 32. The decoder 31 reads have four output ports, three of which are connected.

with the inputs of the second driver 32, | pulses, and the fourth is connected to the input 41 of the installation Of the trigger 33; The output of the trigger 33, the outputs of both pulse formers 32 are outputs of the meter control circuit 29 and are connected to the inputs of the corresponding counter 4..

The device works as follows.

: After the microprocessor system is included in the microprocessor system, the device enters the setup mode. In this mode, the microprocessor system using

5 output commands sets the clock frequency for each of the 4 counters, enables or disables the forlting of microprocessor system interrupt requests after the completion of any of the counters

0 4 and specifies the type of record in each of the counters 4 of the initial state of the account or the type of reading of the state for each of the counters 4. The need to determine the type of record of the initial

The 5 states in the counter 4 or the reading type of the state of the counter 4 are caused by the fact that the microprocessor systems are usually small and 8 or 16 bits. At the same time,. To increase the efficiency of the device as part of the system, it is desirable that the counters 4 have a large size. In this device, the counter size 4 can

5 is twice the size of the microprocessor system in which the device operates. In this case, the initial value may be worn with a single output command.

0 of the microprocessor system only in the older or only in the younger bits of the counter 4. Similarly, a single input command to the microprocessor system can read only the status of the older or only the younger bits of the counter 4.

The control unit 5 provides three types of recording of the initial state. And reading of the state of the counter 4: 1 type of writing (reading) of the lower half of the counter; type 2 - recording (i ning) of the upper half of the bit counts; Type 3 - writing (reading), first of the younger and then the upper half of the counter bits, to two consecutive commands for output (input) of the microprocessor system.

Setting the clock frequency value, enabling or disabling the generation of interrupt requests, selecting the type.

0, the write of the initial state (reading of the state.) For each counter 4 is performed by a microprocessor-based estimate. My separate assignment of control words that come from the system to the device at the inputs-outputs 9-11.

Claims (3)

5 Deitfrator 2 allows transceivers 1 to transfer the control layer through the internal bus 3 to the frequency switch b to determine the clock frequency values for each of the counters 4 or to the trigger 8 to allow or prohibit the generation of interrupt requests after the counters 4 terminate or in the register 28 of the control unit 5 for determining the type of recording of the initial state from the counter 4 or the state 4 reading. After that, the device switches to the initial state loading mode. In this mode, from the microprocessor system at the input-output 9, the device receives the initial state code, which, through the transceiver, sensors 1 and the internal bus 3, enters the inputs of the selected counter 4, recording the initial state to the high or low half of the bits of the counter 4 is produced by recording gates arriving at the corresponding counter 4 via bus 12 from control block 5 (from the output of the OR 3 element of the first generator 32 —in the lower half of the digit of the counter, and from the output of the OR element 38 of the first generator 32 — to the older half of the counter bits). In the case of selecting the third type of loading of the initial state at the third output of the decoder 30 of the recording of the corresponding circuit 29 according to the pulse that is received. em to the first input of the switch 40. Since the flip-flop 39 is initially in the zero state, the pulse from the first input of the switch 40 will go to the first output and then to. the second input of the element OR 37, which will cause the output at the output of the element OR 37 of the write strobe in the lower half of the bits of the counter 4. On the falling edge of the pulse at the third output of the decoder 30 of the recording, the trigger 39 goes into a single state and when it reappears; the third output of the decryptor 30 (i.e. during the second call of the system to the device to write to the upper half of the digit of the counter) the pulse received from the third output of the decoder 30 to the first input of the switch 40 will cause the appearance of a pulse at the second output com 40, which will cause an output at the output of the OR element 38 of the write strobe to the upper half of the digits of the counter 4. When the loading is completed, the device switches to the counting mode. In this mode, the clock impulses of the counters 4 pass through the bus 21 from the commutator 16 to the clock impulses that are transmitted to the switch 16 via the bus 17 from the switch 6 or via the bus 18 from the level normalizer 19. Selection of a particular source tact. output pulses are performed by soldering the bursts in the switch 16. At the input 15, a sequence is fed to the frequency divider 14 from the system. a pulse from which a frequency divider 14 generates several consecutive pulses of different frequencies, for example 1 MHz, 10 kHz, 1 kHz, etc., which are fed to the input of switch b. A sequence of pulses are output to the output of the switch 6. the frequency of which is determined by the control word recorded in the device in the tuning mode. These sequences are supplied to the clock inputs of the respective counters 4. If necessary, the switch 16 can be rebuilt so that the bus 21 is supplied with a sequence of pulses from external sources at the input 20 through the level normalizer 16. The presence of the normalizer 19 allows the clocking of the counters 1): 4 external devices to form pulses, the characteristics of which can vary over a wide range of values. Each pulse arriving from switch 16 to the input of the corresponding counter 4 reduces its contents by one. When occurring in counter 4, the signal from the high discharge at the output of the counter is signaled by a signal. at the output of the trigger 8 at the output of the element 23, the wits interrupt request signal, which is transmitted to the microprocessor system via the corresponding output 24. This means that the time interval read by this counter has expired, and that a new initial state can be loaded into this counter, i.e. the device will go into boot mode. The operation of each counter1 can be suspended by external devices using signals from the normalizer 19 level 19vvn to the inhibit inputs. counters 4. The same signals are simultaneously sent to the inputs of register 7 and their status can be interrogated by the system using the input command via the internal bus 3, which allows: to monitor the status of the signals prohibiting the operation of the counters 4 and determine their duration. The state of each counter 4 can be interrogated by the system using input commands. In order to improve the accuracy of the interrogation of the state of counters 4, before executing the instructions for entering the state of counter 4, the system enters the control word 28 in the control block 5 of the control word 5, which is received by the decoder 31 of the circuit 29. At the fourth output of the decoder 31, a pulse appears. Neither the input 41 of the installation O three Gera 33. From the output of the trigger 33, the potential at the input of the corresponding counter 4 captures its contents which can be edano a system in accordance with a predetermined reading mode. Function, block blocking. 5 control in the read mode is fully consistent with its operation in the write mode of the initial state. At the end of the reading of the state of the selected counter 4, the depotfrater 2 supplies to the input 41 of the flip-flop 33 a pulse, lower. content blocking counter Formula of the invention 1. A device for calculating time intervals of microprocessor systems comprising a transceiver unit, a decoder, a control unit and counters, the first input of the transceiver unit being connected to the information input output of the device, the first and second inputs of the decoder are connected to the address and to the control inputs-outputs of the device, the read-write control outputs of the decoder are connected to the read and write enable inputs the control locus, the outputs of which are connected to the control inputs of the respective counters, the second input-output of the transceiver unit is connected to the information inputs-outputs of the counters and the address input of the control unit, characterized in that it contains a frequency divider, a frequency switch, triggers and elements Both by the number of counters, the level normalizer, the pulse switch and the input register, and the control input of the device is connected to the input of a frequency divider whose output is connected to and The information input of the frequency switch, the control input of which is connected to the second input of the transceiver unit and the trigger setup inputs, the reset inputs of which are connected to the output of the decoder reset control, the trigger outputs are connected to the first inputs of the corresponding elements And the second inputs of which are connected to the outputs of the corresponding counters, B. The elements are connected to the information outputs of the device; the resolution of the frequency switch is connected to the decoder frequency programming output extra. the information input of the device is connected to the input of the level normalizer, the control input of the input register is connected to the control output of the di- distractor iMoM, the first and second inputs of the pulse switch are connected to the outputs of the switch-frequency and the normalizer respectively, the first and second outputs of the pulse switch are connected to the clock inputs and the inputs of the prohibition of counters, and the first and second informational inputs-outputs of the input register are connected respectively to the second input-output of the transceiver unit Cove and the second input of the switch pulses. 2. The device according to claim 1, which is normal in that the normals; the 3 rd level contains rectifiers, filters and optocouplers; the rectifier inputs are connected to the normalizer input, and their outputs are connected to the inputs of the corresponding filters, the inputs of the optocouplers are connected to the outputs appropriate filters, and the outputs of the optocouplers - to the output of the normalizer. 3. The device according to Claim 1, which means that the control block contains a register, write decoders, read decoders, pulse drivers, control triggers, counting triggers, first and second OR elements, and switches by the number of counters, the register input is connected to the address input of the block, and the register output is connected to read and write decoder information inputs, the control inputs of which are connected to the block read and write enable inputs, control trigger outputs, pulse drivers and ale ntov ILIpodklyucheny to block outputs, the outputs of the decoders are connected to inputs read pulse shapers and install O control inputs of flip-flops, the apparatus 1 inputs of which are connected to enable input and read a recording block, first and second output Deshif-. Recorders are connected to the first inputs of the first and second OR elements, respectively, the third outputs of the write decoders are connected to the inputs of the counting triggers and the control inputs of the switches, the first and second inputs of which are connected to the single and zero outputs of the counting trigger, respectively, and the first and second outputs of the switches connected to the second inputs, respectively, the first and second elemental OR. Sources of information taken into account in the examination 1. US patent number 4099232, CL 06 F.1 / 04, published. 1978 2. USSR Author's Certificate No. 547723, KL.S 04 F. 10/04, 1976. 3.Intel component data catalog. .19.79, p. 11-32-11-42. 26 15 T Iq