SU959165A1 - Memory device - Google Patents

Description

(54) RECORDING DEVICE

The invention relates to memory devices and can be used in dynamic memory devices as well as for storing neither analogue or digital information with electrical and optical input.

The known storage device (RAM) contains the first operational amplifier (OA), the analog switch, the storage capacitor, and the second OU, which stores one sample of the analog signal Cl.

The disadvantages of this device are its complexity and the impossibility of simultaneously storing a large number of samples of analog signals. . ,

The closest technical solution to the invention is a memory containing a shift register on devices, with charge coupling, CCD) with output, and input bus, write and read control busbars, first, the transfer control bus of which is connected to the output of pulse generator, the pulse input of which is connected to the output of the transfer control device, the input of the transfer control device

connected to the control bus of the memory device, the second transfer control bus of the shifted register is connected to the power bus 2.

A disadvantage of this device is a large power consumption, due to the large power dissipation, especially at high frequencies that are consumed when charging the capacity of the transfer control bus of the shift register with the help of a key element and during its subsequent discharge during the formation of a rectangular control pulse voltage.

The purpose of the invention is to reduce the power consumed by the device.

The goal is achieved by

20 that a memory device containing a shift register, a pulse shaper and a local control unit, the first output of which is connected to the first input of a pulse body, the output of which is connected to the first transfer output of the shift register, the second transfer output of which is connected and the second control & 30 information and information input and output are respectively the recording control, read control, information input and output of the device, the control key is entered, pulse trimming pulse amplitude and pulse width trimming element, the first output of which is connected to the output of the key control, and the second output - with the output of the pulse former and the input of the pulse amplitude adjustment unit, the output of which is connected to the second input of the pulse former, the first control input the key is connected to the second output of the local control unit, and the second input is connected to the second power bus. The control key contains pnp type control transistors, a pnp type key transistor, resistors and a diode, with the base of the first control transistor connected to the first output of the first resistor and the collector connected to the base of the second control the emitter of which is connected to the zero potential bus, and the collector is connected to the first terminal of the second resistor and the base of the key transistor whose collector is connected to the diode anode, the cathode of which is connected to the emitter of the key transistor and the second leads of the resistors the first- control transistor, the emitter and collector transistor are respectively first and r1m inputs and the output key. The pulse amplitude adjustment unit contains a differential amplifier, a load element, a storage element and an isolation element, the first output of which is the input of the block, and the second output is connected to the first terminals of the load and storage elements and the direct input of the differential amplifier whose inverse input is connected With the bias bus, and the output is, the output of the block, the second terminals of the storage and load elements are connected respectively to the zero potential bus and to the third power bus. The pulse shaper contains the third control and amplifying pnp type transistors and the third resistor, the first output of which is connected to the base of the third control transistor whose collector is connected to the base of the amplifying transistor, the emitter of which is connected to the zero potential bus, and the collector is the output of the block, the first and second inputs of which are the emitter of the third control transistor and the third output of the third resistor. Fig. 1 shows a functional diagram of the proposed device and schematic diagrams of a controllable key, a pulse shaper, and a pulse amplitude adjustment unit; 2 shows timing diagrams for the operation of the device. The memory contains (Fig. 1) a shift register. 1 on the CCD with information input. house 2, output 3, write control input 4, read control input 5, first 6 and second 7 transfer outputs; driver 8 pulses with the first 9 and second 10 inputs and output 11; local control unit 12 with first 13 and second 14 outputs; block 15 adjustment of the amplitude of the pulses; the first 16 and second 17 power tires; a pulse width adjustment element 18, for example an inductive element, and a control key 19. The control key comprises first 20 and second 21 control transistors of a pnp type, key transistor 22, diode 23, first 24 and second 25 resistors . The pulse amplitude adjustment unit 15 includes an isolation element 26, such as a diode, a storage element 27, such as a capacitor, a load element 28, such as a resistor, a differential amplifier 29 with a forward 30 and inverse 31 inputs, and a bias bus 32. The pulse shaper 8 comprises a third control 33 and a power 34 transistors, pn-type and a third resistor 35. In Fig. 1, the device input 36 is started. FIG. 2 denotes: voltage levels Ujj, at device input 36, voltage levels U-j and voltage pulses u / j, respectively, at outputs 14 and 13 of unit 12, voltage pulses U and voltage level U-; respectively, at outputs 6 and 7 of register 1, the supply voltage level and 2 on the power bus 17, the voltage and the collector of transistor 22, the lower voltage level UH, the law of change of current i in the element 18. The described memory operates as follows. In the storage mode of the information, the output 6 of the register 1 maintains the voltage level and, determining the lower level of the transfer control pulses O, the output 7 is under a higher storage potential U-J. In this case, the information charges are localized under the electrodes connected to the output 7 of register 1. At some instant of time tg (Fig. 2) to the inputs 4 of the write control and 5 of the read control

(Fig. 1) a signal is received to start recording information, which enters input 2 (or starts reading information from output 3). At the same time, a control pulse is applied to the device input 36. At the output 14 of the block 12, a pulse is formed, which is fed to the input of the key 19 and closes it. In this case, the element 18 is connected via a closed key 19 to the power bus 17 with a voltage V. A shock excitation of an oscillating circuit formed by the element 18 and a parasitic transfer control bus capacitor connected to the output 6 occurs.

To ensure a continuous process of oscillations in the circuit from the output 11 of the former 8, current pulses with a repetition frequency determined by block 12 equal to the resonant frequency of the circuit ujp are applied to the output (subharmonic frequencies are possible, i.e. bUp / 2, hf / 3 and t .d.) The amplitude of the current pulses at the output 11 is controlled by the block 15, which is maintained on. input 1-0 shaper 8 required potential. A dial that provides 6 continuous oscillations at the output.

The transfer of information in register 1 occurs, as well as the recording and / or reading of information depending on the state of inputs 4 and 5.

The transfer of the storage device to the information storage mode is effected by a signal input to input 36 of block 12. At time t, when the current in the -18 element is zero, and the transfer control output 6 is equal to UH / control key 19 by the output signal 14 is opened and the voltage fluctuations at output b are stopped, and the pulses at output 13 of block 12 are interrupted. Block 15 has memory, therefore, the amplitude values of the voltages of subsequent control oscillation groups at output 6 are set almost from the first oscillation.

The condition of reading part of the information stored in the memory, without distorting the remaining information, determines the requirements for the form of voltage oscillations at the output 6. The presence of residual oscillations after a moment of time can lead to the destruction of part of the information charges of the packets or mutual overlap distortions. charge packets stored in the neighboring CCD cells of register 1. In addition, if the key is opened at the moment of

„2Ji

t t + & t, where DC "T - p"

2Jin

then in elep - 1, 2, ...

 0 + Shr

At 18, self-induced emf occurs. It can disable the controllable key 19, which reduces the stability requirements of the moment the pulse ends at its first input;

t. ,, 0. At, .-.

. KLK1CH 19 works as follows.

In the initial state with

0 the first output of the key 19 is zero potential, the transistor 20 is saturated, the transistors 21 and 22 are closed (the key 19 is open). At time t to, the emitter of the transistor 20 is supplied

5, a single logic signal and the emitter junction is closed. The current of the resistor 25 unlocks the transistor 21, the collector current of which creates a voltage drop across the resistor 24

0 saturating transistor 22. At the collector of transistor 22, the voltage abruptly changes to

, Urj and,: ,, where OKH is the saturation voltage of the transistor 22. Begins

5 charge of the parasitic bus capacitor with a transfer control at the output 6 of the current flowing from the power bus 17 through the saturated transistor 22 and the element 18. At the moment when the voltage across the capacitor C reaches

values of P / 2, the current in element 18 is maximum, and the further charge of capacitor C occurs due to the energy of the magnetic field stored in the inductance of element 18. After

5 as the voltage across the capacitor C reaches the maximum value, the current in the element 18 changes direction. The discharge of capacitor C begins. In this case, the current flows through the saturated

0 transistor 22 and open diode 23. If during the time when capacitor C discharges, transistor 22 turns on, the discharge continues through diode 23 and at the end of the research institute of the discharge voltage oscillation at the output 6 stops .0

The block 15 and the imaging unit 8 operates as follows.

In the transfer mode information

0 charge packets along register 1 on drive 6 are supported by a continuous oscillatory process. If the minimum voltage values at output 6 are greater than

Claims (2)

5, the potential on the supply bus 32 (bias voltage), the diode 26 does not open, and the capacitor 27 is charged through a resistor 28 to a voltage corresponding to the minimum voltage level at the output 6. At the output of the amplifier 29, an increased potential difference appears, on its inputs are 30 and 31 with a plus sign. At the same time, the collector current pulses of the transistor 34 in the driver 8 increase in amplitude, and the amplitude of the voltage oscillations at the output b of register 1 increases. The adjustment of the amplitude of the control oscillations occurs until the minimum value of the voltage at the output b equals voltage on bus 32 (bias voltage), If the time constant of the capacitor circuit 27 - the resistor 28 is much longer than the maximum storage time of the memory device, then the mode of the block 15 does not change much during M9 pauses between the series of control signals oscillations have a constant amplitude.,. The power consumed by the device from the power source is reduced due to the oscillatory periodic redistribution of energy from the electric field of the capacitor C of the transfer control bus at the output 6 of register 1 to the magnetic inductance of the element 18 and vice versa. The technical and economic advantage of the proposed device consists in reducing, as compared with the prototype, power consumption. Claim 1. A memory device containing a shift register, a pulse shaper, and a local control unit, the first output of which is connected to the first input of the pulse shaper, the output of which is connected to the first transfer output of the shift register, the second transfer output of which is connected to the first The power bus and the first and second control and information input and output are respectively the write control, read control, information input and output control devices of the device, characterized by In order to reduce power consumption, it contains a controllable key, a pulse amplitude adjustment unit and a pulse width adjustment element, the first of which is connected to the output of the controllable key, and a second pin with an output of the pulse amplifier and the pulse amplitude adjustment unit, the output of which It is connected to the second input of the pulse generator, the first input of the controlled key is connected to the second output of the local control unit, and the second is connected to the second power supply. 2. The device according to claim 1, of which the control key contains pn-type control transistors, a key transistor, resistors and a diode, the base of the first control transistor connected to the first output of the first the resistor, and the collector is connected to the base of the second control transistor, the emitter of which is connected to the zero potential bus, and the collector is the first terminal of the second resistor and the base of the key transistor, the collector of which is connected to the anode of the diode, the cathode of which is connected to the emitter of the key transistor and The second terminals of the resistors, the emitter of the first control transistor, the emitter and the collector of the key transistor are respectively the first and second inputs and the output of the key. 3. The device according to claim 1, which implies that the pulse amplitude adjustment unit contains a differential amplifier, a load element, a storage element and a decoupling element, the first output of which is the input of the block, and the second output is connected to the first load terminals and the storage element and the direct input of the differential amplifier, the inverse input of which is connected to the bus mix. and the output is the output of the block, the second terminals of the accumulative and load cells are connected respectively to the zero potential bus and to the third power bus. 4. The device according to Claim 1, which includes the pulse shaper comprising a third pn-type control and amplifying transistor and a third resistor, the first output of which is connected to the base of the third control transistor, the collector of which is connected to The base of the amplifying transistor, the emitter of which is connected to the zero potential bus, and the collector is the output of the block, the first and second inputs of which are respectively the emitter of the third control transistor and the second output of the third resistor. Sources of information taken into account in the examination 1. Analog integrated circuits. Ed. J. Conmely. I., Mir} 1977, p. 281. 2. Patent SHE number 4216386, cl. 307/221, published. 1980 (prototype). 3S