SU959091A1 - Digital correlator for detecting echo-signal - Google Patents

Description

(54) DIGITAL CORRELATOR FOR DETECTION OF ECHO SIGNALS

. The invention relates to the field of specialized computing equipment intended for the mutual correlation processing of echo signals.

There are known AFR correlator containing, frequency-pulse converter, logic blocks, Delay unit, reversible counters flj.

However, this correlator is not characterized by a high signal-to-noise ratio.

Iziesten also correlated TRP contents. Two delay units, an arithmetic unit accumulating adder and a control unit t2j ";

The disadvantage of this corrector is that the processing of cHt of the cath (reference and input) is identical, since the thinned samples of the reference signal are recorded in the first delay unit, and the uncleaned samples of the input signal from the second delay block are pre-accumulated before the arithmetic unit. This leads to a decrease in the truncation of the computation of the ordinates of the mutual correlation function (ICF) V, at which the error values are different in the formation of various probe signals. In addition, the processing of non-continuous signals or signals of considerable duration requires continuous updating of the memory of not only the second, but also the first delay unit.

The purpose of the invention is to improve the accuracy of computing the ordinates of the CCF and the divergence of functional capabilities.

10 Correlle Torah

The essence of the invention lies in the TOi, which ensures the identical processing of the input and reference signals including the continuous updating of information in the corrector of the torus.

The goal is achieved by the fact that, in the digital correlator xor of the detection of echoes, containing the first

20 and the second delay block, whose inputs are the first and second inputs of the correlator, respectively, to the output of the second delay block are connected to the nepBOJTo input of the accumulating sum25 of the mat, whose output is connected to the first input of the arithmetic block, synchronization inputs of the arithmetic block and accumulator of its adder are connected to the First to the output of the control unit of the 30th equipo nt whose output is central with the control inputs of the delay units, a second accumulating adder is introduced, the input of which is connected to the output of the first delay unit od vtsorym connected to the input of the arithmetic unit, and input sinhronieatsii nakaplivayschego second adder connected to the first control unit.

FIG. 1 shows the digital correlating circuit diagram of FIG. , 2 - block diagrams of the arithmetic unit and the control unit. The correlator contains two delay units 1 and 2, two sum accumulating matrices 3 and 4, an arithmetic unit 5 and a control unit 6, the first output of which is connected to the synchronization inputs of the accumulating adders 3, 4 and the control input of the unit 5, the second output of the control unit b is connected to the control inputs of the delay units 1 and 2, the output of the block 1 is connected via the accumulating adder 3 to the first input of the block 5, and the output of the block 2 is connected via the accumulating sum torus 4 to the second input of the arithmetic block 5. J

FIG. Figure 2 shows the structural diagrams of the arithmetic unit 5 and the control unit 6 for the case when random access memory devices (RAM) are used as delay units 1 and 2, respectively.

The arithmetic unit 5 contains a serially connected unit of multiplication 5 | and the accumulator implemented on the combinational adder and the GZ memory element. The output of the element 5e is connected to the output of the correlator and with the second input of the combinational adder 5.

The control unit 6 contains a generator of 6 clock pulses, an address counter 6, the outputs of which are connected to the address inputs OZU1 and OZU2, a score 1ik 6 of the Write-Read commands, the output of which is connected to the control inputs OZU1 and OZU2 and a synchronization counter 64, the output of which is connected to the synchronization inputs of the multiplication unit 3v and accumulating adders 3 and 4 of the correlator.

The counter of 6 addresses is reset by the N-i input pulse, the counter 6 Write-Read has null cjf by the input pulse.

Thus, it is provided in-g sequential recording of the input information in cells PS1 mi OZU1 and OZU2

 64 synchronization is zeroed by the input pulse, fixing the beginning and the end of the interval of preliminary summation by accumulating adders 3 and 4 of the corrector.

For the case of N 4048 and I 4-8, the arithmetic unit and the control unit are not implemented on the IC 133 series.

Delay blocks 1 and 2 are implemented on RAM 505 Ru.

The operation of the digital correlator is as follows.

Delay blocks 1 and 2 with memory N continuously receive unspent samples of input and reference signals. For the time between two adjacent samples arriving at the input. the correlator of the torus, polls blocks 1 and 2, and the polling rate of both delay blocks is the same. From their outputs, the samples are fed to the corresponding inputs of accumulating adders 3 and 4, which perform the current summation over samples from blocks 1 and 2, respectively. The results of the corresponding summations form a pair of samples, which enters the arithmetic unit, where you are. Borks forming a pair are multiplied, followed by summation over the averaging interval. Thus, in the time between the two samples sequentially arriving at the input of the correlator, a complete interrogation of the memory of delay unit 1 and 2 and the formation of N / E pairs of samples were made, the samples of the pairs were multiplied, and the result of the multiplication was averaged. The computation of the next ordinate of the CCF occurs in the next interval between the input samples arriving at the input by a similar method, while the sample itself is. Ps1m ti delay units 1 and 2 are replaced by the newly arrived. The calculation of the CCF occurs continuously, the information is removed from the output of the correlator in the rate of arrival of the input samples, m; e. the correlator provides input signal processing on a real time scale. The control unit of the proposed device is similar to the known one. The delay between the input and reference signals can be changed using an additional delay device (not shown in Fig. 1).

The use of this device will make it possible to realize higher accuracy parameters of detection and analysis and expand the functionality of the signal processing path.

Claims (1)

Invention Formula A digital correlator for detecting e, ho-signals containing first and second delay blocks whose inputs are the first and second inputs of the correlator, respectively, the output of the second delay block connected to the input of the first accumulating adder whose output is connected to the first input of the arithmetic block, arithmetic sync inputs the block and accumulating adder are connected to the first output of the control unit, the second output of which is connected to the control inputs of the delay units, characterized in that, in order to improve accuracy, the second accumulating adder is input to the correlator, whose input is connected to the output of the first delay block, output connected to the second input of the arithmetic unit, and the input synchronization of the second accumulating adder is connected to the first output of the unit of the eurenization. i Sources of information taken into account in the examination 1, Zhovinsky V.N., Arkhovsky V.F. Correlation devices. M. Energie, 1974, p. 142 2, USSR Author's Certificate in Application No. 2876354 / 18-24, cl. G 06 F 15/336, 1979. / tiftt Crash amm1m | «, CuMfH ite e