SU959082A1 - Multi-channel priority device - Google Patents

Description

(54) MULTI-CHANNEL PRIORITY DEVICE

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The invention relates to the field of automation and computational engineering. ki, in particular to the organization of systems of interruption and control of data transmission.

A multi-priority device is known that contains a query indication register, an auxiliary register, and AND gates.

A disadvantage of this device is considerable complexity.

The closest in technical essence to the invention is a multichannel priority device consisting of vi channels, each of which contains the first and second AND-NOT element, as well as the AND and.

However, this device is characterized by insufficient noise immunity, since it is possible for the device outputs to emit short signals at the moment when the polling signal arrives at the control input without the request being present at the corresponding inputs.

The purpose of the invention is to improve the noise immunity of the device.

The goal is achieved by the fact that in a multi-channel priority device containing both channels, and in each channel, the first and second elements are NAND, the AND element and the first element are NOT, the first inputs of the first elements of each channel are connected to the corresponding request inputs of the device, the outputs

10 AND elements of each channel are connected to the corresponding outputs of the device, the first inputs of the AND element and the second element AND –NE of the first channel v are connected to the clock input of the device;

15, the output of the second NAND element: each channel through the first element of its own NOT channel is connected to the first input of the second NAND element of its channel and to the first

20 input element And the next channel; the output of the second NAND element of each channel is co-amped with the second input of the first NAND element of its channel, the output of the first NAND element

25 each channel is connected to the second input of the second element AND-NOT of its channel, the second element is entered in each channel; its input is NOT connected to the output of the first element of the channel IS-NOT, and the output is connected to the second input of the AND element of its channel. The drawing shows a block diagram of the device. The device contains the elements AND-NOT 1,2, the elements HE 3, 4, the elements AND 5, the clock input b of the device, the request input 7 of the device, the outputs 8 of the device, the channels. The device works as follows. The first and second elements AND-NOT 1,, 2, interconnected according to the trigger scheme with separate inputs, work as a logical selection circuit of one of two asynchronous signals at its inputs 6,7. If there are no signals at the first inputs of the NAND elements of the first channel (low potential), the outputs of these elements have high potential levels, which corresponds to the state of the logical unit. When a clock polling signal arrives at the input b of the device, while the request signal at input 7 is absent, the clock signal passes to the output of the NAND element 2 of the first channel - a low potential level and further to the output of the HE 4 element and control input | the next highest priority channel. At the same time, the output of the first channel IN-1 element is blocked by its second input by a low potential level, so that, starting from this moment, the request signal in this channel cannot pass to the output of the AND-NOT 2 element and the HE 3 element, and therefore , to the second input of the And 5 element. At the same time, the clock signal polls the And 5 element, but since the second input of this element has a low potential level, the input state of the And 5 element and therefore this priority channel does not change. The clock signal arriving at the control input of the next priority channel continues to propagate along the circuit of the control inputs of the channels until it surrounds the channel that has a request at the input. The signal (high level of potential), which arrived before the clock signal at the control input) of the channel, passes to the output of the N-1 element of this channel by the negative potential and then through the element NOT to the second input of the And 5 element with high potential. At the same time, the output of the AND-HE 2 element is blocked by the second input, so that, starting from this moment, the initial output state of the AND-HE element 2 cannot change when the clock signal arrives at its first input. Therefore, the clock signal does not propagate further, but changes the output state of the element AND 5 of this channel, since the second input of this element has a high potential level. Thus, the clock signal applied to the device input propagates along the circuit of the control inputs of the channels in the absence of request signals at their inputs, at the same time blocking these inputs and opra; beer elements 5 at the channel outputs. Distribution is made up to the i-th channel, at the input of which there is a request. By polling element 5 in this channel, the clock signal changes its state from low to high, which corresponds to the allocation of the highest priority request signal. Ib, since in all previous channels (senior in priority) priority inputs are blocked, and the control inputs of all subsequent channels (lower priority) do not propagate the polling signal, requests in these channels cannot pass from inputs 7 to outputs B during the whole service request time. At the same time, pings with a number greater than i (i.e., the lower ones by priority are not served even if they are received simultaneously or even before the i-th request. If, after the removal of the 1st request, the clock signal is not cleared yet the control input of the device, its propagation continues, starting with the channel just served, towards the channels with lower priority, among which the first order channel with the request for its input is searched. The distribution of the clock signal in this device is not accompanied by a selection of short seconds. This is achieved by the fact that the second input of the AND5 element is connected through the NO 3 element to the output of the IS-1 element 1. Consequently, the state of the second input of the AND 5 element at the moment of influence on its first input, the polling signal does not change and has a logical zero value. As a result, the outputs of the priority channels remain reliably blocked. Thus, the application of the invention eliminates the appearance of spurious signals on the device inputs. during the propagation of a clock pulse, which increases the noise immunity of the device.

Claims (2)

1. Authors certificate of the USSR 425177, cl. G About F 9/46, 1974. 2. Authors certificate of the USSR 544967, cl. G 06 F 0/46, 1977 (prototype).