SU945973A2 - Pulse duration discriminator - Google Patents

Description

(54) SELECTOR OF PULSES OF DURATION

The invention relates to a pulse technique and can be used in automated information-measurement and control technology systems for various purposes.

According to the main author. St. The Mi 687579 is known for an impulse selector with respect to polarity, which contains an differentiating element, a precision generator, a clock generator, a pulse counter, a decoder, a control valve, a time interval counter, a zero detector, and a scaling device. This selector allows the selection of pulses of variable duration in a dynamic mode of monitoring the input sequence, the duration of which is a multiple of the value of the reference interval Cl.

A disadvantage of this device when used in automated information-measuring systems is that it does not allow the selection of pulses, the duration of which in the sequence is given by fixed priority. This disadvantage is due to the lack of the possibility of prioritizing the reinstallation of the reference inter & ala, depending on the number of the selectable interval, which, in turn, narrows the scope of its use.

The purpose of the invention is the expansion of functional capabilities by means of selection and selection of variable time intervals on the basis of priority depending on their sequence number in the dynamic mode of monitoring the input signal sequence.

Claims (1)

The goal is achieved by the fact that the pulse selector has a duration, containing a differentiating element, a precision setting generator, a clock pulse generator (GGI), a pulse counter whose output is connected to the first input of the oscillator, and an adjusting input is connected to the first OUT of the controlled valve, the counter the multiplicity, the detector zero, the out-alignment device, the first output of which is connected to the output bus, the second input through the detector zero is connected to the first control input of the GTI, the second control input of which is connected to B brxoiw of the differentiating element and the first input of the controlled valve, the third control input is connected to the second output of the control valve, the installation input of the multiplicity counter and the first input of the scaling device, the first output is connected to the counting counter of the pulse counter, the second output to the second input of the scaling device, the third input of which through the counter of multiplicity of switches to the second input of the controlled valve and the output of the decipher, the input of which is connected to the OUTPUT of the accuracy sensor, is entered sequentially The cyclic shift, the first input of which is connected to the second cop of the clock, and the second - to the output time slots multiplicity counter unit detecting discharge priority and priority counter whose output is connected to the input zadagchika accuracy. FIG. Figure 1 shows a structural electrical circuit of a pulse selector for duration; in fig. 2 - in | eemennye diagrams, explanatory work, devices .. Pulse selector by duration contains differentiating element I, intended to form reference signals Start and End Y - analyzed time intervals; a clock pulse generator 2 generating a counting sequence with a constant period tjj, a control valve 3, a pulse counter 4, a decoder 5, a precision setting device 6, a cyclic shift register 7, a time interval multiplicity counter 8; scaling unit 9, priority detecting unit 10, priority counter 11, detector zero 12, 13 and 14 are respectively input and output devices of the device. FIG. 2, 2a - input binary sequence of signals of variable duration T – C, variable distance between them; b - the sequence of reference signals of the Beginning and Kc ets; 2c shows the continuity of clock pulses with a constant follow-up period; 2g - code transmissions of Nj durations of the analyzed signals; 2c- signals of multiplicity of time intervals; 2e - signals of the same multiplicity pulses and signals End; 2g - output selected pulse sequence; Pulse selector in duration works in a consistent manner. Upon receipt at the input 13 of the binary sequence of the signal JJOB (Fig. 2 a) differentiating element 1 generates the reference signals (fig.2b), corresponding to the signals of the Beginning and the End of each incoming pulse T. These signals are fed to the input of the generator 2 and at the same time the output input of the control valve 3. The generator 2 has two frequency outputs that produce counting pulses of stable frequency (Figure 2b). With the arrival of the Start signal from the first frequency signal, the pulses arrive at the input of counter 4, which converts the counting sequence into a parallel binary code (Fig. 2d). Such a mode of operation of the device is preserved until a signal arrives at oscillator 2, which disconnects the first frequency output. Simultaneously with the accumulation of counting pulses in counter 4, decipher 5, a continuous dynamic comparison of numbers expressed in the form of a variable numeric code N is performed; counter 4 with a fixed M code. The settings previously recorded in the setter 6. The code for the initial setpoint is selected based on a priori knowledge of the parameters of selectable durations and is determined by the corresponding bit number of the cyclic shift register 7, which has the highest priority at the moment. In case of equality of the code values N and M: at the output of decipher 5 An equal signal is generated (FIG. 2d), which is fed to the second input of the control valve 3 and simultaneously to the VDK 8 account. The control valve 3 is dependent on the temporal distribution of the incoming signals and the End (FIG. 26) and the equal signals (FIG. 2 e) produce control signals Reset and Enable and Disable. B, when the code of the time interval of the analyzed duration T. is equal to the braid Mj behind sensor 6 or is a multiple of it, i.e. when N., at K 1,2,3 ...), the signal of the End signal and the equality signal coming from the decoder 5 coincide. As a result of this coincidence, the control valve 3 generates the Permission signal (Fig. 2e), which the control inputs of counter 2 for content census to scaling unit 9, and register 7. At the same time, the value is reset in the setter fc and the second frequency output of oscillator 2, associated with scaling unit 9 and cyclic register 7, is opened. Under these conditions, code of new setting iM.M on addr ECU, which has the next priority. When receiving from generator 2, the counting sequence is. The number of pulses on the cyclic register 7 begins to shift towards the higher bit. At the same time, after each clock cycle of the priority discharge block 10, the current state of a certain bit of register 7 set by the counter code 8 is analyzed. When the bit is in zero, I is added to the counter 11 when the bit of the analysis of the unit is analyzed by the block Yu, it stops The new content in counter 11 is used with the modulated part of the address of the code setpoint formed by the preset 6. Thus, the code in the counter 11 determines the address of the variable setpoint value generated by the next priority. At that, the number of priority positions corresponds to the size of the cyclic register 7. Simultaneously with the formation of the next priority address, the output information is formed by reading in the reverse code in the scaling unit 9 by a sequence of clock pulses from the generator 2 until reaching the zero state, which is fixed by the zero detector 12 The output signal of the detector zero 12 is turned off by the second frequency output of the generator 2 and the information from block 9 goes to the output bus 14 (Fig. 2k). In section C. When the analyzed interval T, is not a multiple of the reference interval, the signals of the End and Equality will not coincide. In such measurement situations, the control valve 3 generates a B1 reset command, and with the arrival of the Start signal, the counter 4 and counter 8 are cleared without entering the accumulated value into block 9 and the register 7, With the arrival of each subsequent reference signal, the device is ready for reception and processing subsequent analyzed duration. Thus, the introduction of a cyclic shift register, a priority selection block and a priority counter into the device allows the device to expand its functional capabilities by providing variable time intervals based on priority depending on the order number in the dynamic control mode of the input binary signal sequence. Claims of the invention Pulse selector by duration according to aut. St. Ni 687579, characterized in that, in order to expand () the unique capabilities by providing selectors of variable time intervals on the basis of priority, depending on the sequence number, in a dynamic control mode of the input signal sequence, the first-connected cyclic shift register is entered into it which is connected to the first output of the clock pulse generator, the second input is connected to the output of the multiplicity counter of the time intervals, the block for detecting the priority bit in the counter p ioriteta whose output is connected to the second input of the setpoint accuracy. Sources of information taken into account in the examination 1. USSR author's certificate Nf 687579, cl. And OZ K 5/18, 08.28.79 (prototype). . . -.