SU531270A1 - Device for fixing random signal centers - Google Patents

Description

with the third output of the control pulse generator.

The drawing shows a structural electrical circuit of the device.

A device for fixing random signal centers contains a shaping threshold element 1, the output of which is connected to the input of a control pulse generator 2 and to the input of a shift register 3 connected by one of the outputs to a single input of a control trigger 4, detector zero 5.

The output of the control pulse generator 2 through the delay element 6 is connected to the signal input of the control key 7, the control input of which is connected to the single output of the trigger 4, the zero input of which is connected to the output of the detector zero 5, and the output of the key 7 is connected to the counting input of the delayed counter signals 8, a single input of which is connected to one of the outputs of register 9 for storing the code of the next center, the output of the counter of delayed input signals 8 through the serially connected detector zero 5, register 9 for storing the code the next center, the counter of input random signals 10 and the frequency divider by two 11 are connected to the third output of the control pulse generator 2

To ensure the operation of the device, the circuit has an input 12 for supplying an input pulse sequence, a frequency divider 13 with a variable division factor, an output 14 and an input 15 for giving a measurement command.

A device for fixing random signal centers operates as follows.

The input signal sequence is fed from input 12 to the forming threshold element 1, which generates square-wave signals from them and determines the beginning and end of each input signal.

Control pulse generator 2 has two frequency outputs.

The first frequency output provides highly stable pulses arriving at the input of the frequency divider by two 11 in the presence of a command to measure at input 15 and, when the formative threshold element 1 selects a pulse of the beginning of the incoming signal. With the arrival at the end of the signal from the forming threshold element 1, the first frequency output is switched off. The second frequency output depends on the measurement command, which allows the arrival of highly stable pulses at the input of delay element 6 and frequency divider 13 with a variable division factor. Thus, the first frequency output transmits a time interval equal to the duration of the input signal to the frequency. In addition, the control pulse generator 2 controls all the nodes of the device.

The frequency divider into two 11 produces a division of the pulses of a stable frequency. During the duration of the incoming signal from the output of the frequency divider by two 11, a series of pulses is formed with a period twice as short as the input sequence. This series of pulses is fed to the input of a counter of input random signals 10, which serves to

converting a series of pulses from the frequency divider by two 11 into a parallel unitary binary code.

The outputs of the counter 10 are associated with the installation inputs of the register 9 for storing the code of the next center. The counter 10 is reset after the received code is transmitted to the register 9 by signals from the control generator 2, which conducts a continuous analysis of the state of the register; 9 is busy.

Register 9 receives from the counter 10 the code of the next center and stores it until the next

into the counter of delayed input signals 8. The code from register 9 is signaled by a center signal, which appears at the output of detector zero 5. After issuing the code, register 9 is set to the zero state.

Shift register 3 is designed to delay the selected pulses at the beginning of each input signal. For this, the input of shift register 3 is connected to the signal output of the beginning and end of the control pulse generator 2. According to the device operation algorithm, the signal of the end of the signal is not used. Therefore, with the arrival in the shift register 3, it is quenched.

In order to obtain high accuracy of the delay time, the information in the shift register 3 is shifted by stable frequency pulses, which are fed to the control input of the shift register 3 from the output of the frequency divider 13. The total delay time includes the delay time of the shift register 3 and the delay time of the frequency divider 13. the trigger 4 controls key 7. With the arrival of the pulse of the signal from the output of the shift register 3, the control trigger 4 is set to one state by applying a permitting potential to the key 7. In this case, the stable frequency pulses from the output of the control pulse generator 2 through the delay element 6 and

kpuch 7 are fed to the counting input of the counter delayed input signals 8.

Delay element b is used to delay ir, stable frequency shunts for the trigger time 4.

The delayed input counter 8 is used to convert a consistent series of stable frequency pulses into a code. He works on subtraction. By the time pulses arrive at counter 8, the code of the next center is entered from register 9. Therefore, the code in counter 8 will decrease. Detector zero 5 determines the zero state of the delayed input signals counter 8. The selected center signal sets the trigger 4 to the zero state, prohibiting the arrival of pulses in counter 8. At the same time, this signal enters register 9, allowing its next center code to enter counter 8. The signal center is fed to the output 14 of the device.

Claims (2)

1. Kaverkin I. Ya. And Kharitonova 3. V. A device for distinguishing the extreme values of measured signals. Sat Automation of electrical measurements, M., ONTIPribor, 1966. 2. UK Patent No. 1267О26, cl. H 03 K 5/18, H 03 K 5/153, publ. 03.15.72 (prototype). 35 75 0 / 2