SU945887A1 - Device for displaying static characteristics of an object on crt screen - Google Patents

Description

one

The invention relates to computing and measuring technology and can be used for visual indication of input, transfer and output characteristics of lines and digital electronic circuits of potential type with simultaneous measurement of their static parameters.

A known device for displaying information comprising a keyboard connected to a control unit connected to a memory unit, a graphic element generator and a shift register connected to a television receiver 13.

A disadvantage of the known device is the low accuracy of information display. N

The closest technical solution to the invention is a device for visually and analyzing the static characteristics of potential type circuits, which consists of t

a measuring voltage shaping circuit, a measuring resistor, a circuit being analyzed, a differential amplifier, four analog switches, a key management device, a frame interceptor device, a frame horizontal displacement device, and a electron-beam tube with a sum (1

, d amplifiers for vertical and horizontal deflection. The output of the measuring voltage shaping circuit is connected to the first output of the measuring resistor and the first input of the differential amplifier, the second output of the measuring resistor is connected to the input of the analyzed amplifier, to the second input of the differential amplifier and the analog input of the third

20 analog key. The output of the differential amplifier is connected to the analog input of the first analog switch. The outputs of the first and second analog switches are interconnected 3E and with the input of the sum of the amplifier vertical deflection. The outputs of the third and fourth analog switches are connected to each other and to the input of a horizontal deflection amplifier. The control inputs of all analog switches are connected to the corresponding outputs of the key management device. In this charatograph, a transformer with an adjustable output is used as a circuit for measuring voltage, a vertical oscillator of an electronic oscilloscope with differential inputs is used as a differential amplifier, and interrupt switches, for example, contact groups of a polarized relay, as four analog switches. , as a key management device, a polarized relay winding is connected to the same network to which a transformer with an adjustable output is connected However, distortion of the type of beam astigmatis does not allow the operator to set the reference point to the required place of the characteristic, which reduces the measurement accuracy. In addition, the drift zero of summing amplifiers of vertical and horizontal deviations shifts the characteristic under investigation relative to the coordinate pines of the motionless grid of the oscilloscope scale, which worsens the conditions of the operator’s work, since be balanced amplifiers and combining null beam deflection with the coordinate scale grid. In addition, the gain of the summing amplifiers of the vertical and horizontal deviations does not allow the operator to perform accurate measurements using the fixed scale of the oscilloscope, which worsens the conditions of its operation, since it needs to periodically calibrate the sensitivity of the amplifiers. The aim of the invention is to improve the accuracy of measurement of parameters of static characteristics. The goal is achieved by the fact that the device for displaying the static characteristics of an object on the screen a 74 is not a CRT, containing a measuring voltage shaping unit, a measuring element, a differential amplifier, four analog keys, a key control unit, a frame of the frame offset in the vertical direction, a frame of the frame offset horizontally summing amplifiers of vertical and horizontal deflection, with the output of the forming unit of the measuring element and the first input of the differential amplifier, the second output The element is connected to the input of the device, with the second input of the differential amplifier, the output of the differential amplifier is connected to the analog input of the first switch, the outputs of the first and second switches are connected to the input of the summing amplifier of vertical deviation, the outputs of the third and fourth switches are connected to the input of the summing amplifier of horizontal deflection, control the inputs of all the keys are connected to the corresponding outputs of the key management unit, the analog input of the third key is connected to the input of the device, It contains series-connected clock generator, reversible binary counter, binary counter, code converter and first digital-to-analog converter (D / A converter), voltage divider, scale forming unit, horizontal scale displacement unit, horizontal displacement unit, generator sinusoidal and cosinusoidal; apr, the unit of changing the levels of sinusoidal and cosinusoidal stresses, four summing amplifiers, the fourth, fifth, sixth and seventh my, eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth keys, summing amplifiers, a second DAC with the outputs of the bits of the reversible binary counter connected to the digital inputs of the first DAC, the outputs of the binary counter connected to the inputs of the key control unit, the output of the block the scale formation is connected to the first inputs of the first and second summing amplifiers, the second input of the first summing amplifier is connected to the output of the horizontal scale offset block vertically, the second input of the second sum The power amplifier is connected to the output of the vertical scale offset unit horizontally, the outputs of the sine-wave and cosine-oscillator generators are connected to the inputs of the sine-wave and cosine-sided levels generator, the output of which’s sinusoidal signal is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier, and the cosine-shaped output of which is connected to the first input of the third summing amplifier the first input of the fourth summation amplifier, the second input of the third summing amplifier is connected to the output of the frame of the frame of reference of the vertically, in The second input of the fourth summing amplifier is connected to the output of the reference frame of the reference frame, the output of the second DAC is connected to the input of the voltage divider, the input of the measuring voltage shaping unit and the analog inputs of the sixth and eleventh keys, the analog inputs of the fifth and ten keys are connected to the output the first DAC, the analog inputs of the seventh and twelfth keys are connected to the output of the voltage divider, the analog inputs of the eighth and thirteenth keys are connected to the zero potential bus, the analog input to The key is connected to the output of the third summing amplifier; the analog input of the fourth key is connected to the output of the fourth summing amplifier; the analog input of the ninth key is connected to the output of the first summing amplifier; the analog input of the fourteenth key is connected to the output of the second summing amplifier, the control inputs of all keys connected to the corresponding outputs of the control unit with the output keys of the fifth, sixth, seventh, eighth and ninth keys connected to the input of the summing amplifier About the deflection, and the outputs of the tenth, eleventh, twelfth, thirteenth and fourteenth keys are connected to the input of the summing amplifier of horizontal deflection. FIG. 1 shows a functional circuit; FIG. 2 — time diagrams of voltages acting on deflection plates of the oscilloscope CRT, time diagrams of the operation of the key control device and time diagrams of the binary counter operation; in fig. 3 - a picture formed by an electron beam on an oscilloscope's CRT screen, with a fixed scale grid removed, located in front of the CRT screen. (To protect the CRT from mechanical damage, a clean plate can be installed instead of a removed plate with a scale). The device contains a clock pulse generator 1, a reversible binary counter 2, a second D / A converter 3, a voltage divider k, a scale formation unit 5, a horizontal scale vertical displacement unit 6, a vertical scale offset 7 unit, a sine-wave cosine and cosine-voltage generator 8 two corresponding outputs, block 9 of changing the levels of sinusoidal and cosine voltage, binary counter 10, converter 11 codes, first D / A converter 12, first summing amplifier 13, second summing amplifier T, b vertical frame offset 15, horizontal frame displacement block 16, measuring voltage generation unit 17, key management unit 18, differential amplifier 19, third sum iruyy amplifier 20, fourth summing amplifier 21, analyzed object 22, from fifth to eighth keys 23-.26-, second key 27, ninth key 28, first key 29, tenth to thirteenth keys 3U-33, fourth key fourteenth key 35, third key 36, summing amplifier 37 vertical deflection and summing amplifier ZV go : risky deviation, w Inu 39 and measuring element kO. The output of the generator t of clock pulses is connected to the input of the reversible binary counter 2 and to the input of the scale generation unit 5. The output of the reverse binary counter 2 is connected to the input of the binary counter 10. The outputs of the bits of the reverse binary counter 2 are connected to the digital inputs of the second DAC 3. The outputs of the bits of the binary counter 10 are connected to the inputs of the code converter 11 and the key control unit 18. The outputs of the converter 11 codes are connected to digital inputs of the first DAC 12. The output of the scale forming unit 5 is connected to the first inputs of the first 13 and second And summing amplifiers. The second input of the first summing amplifier 13. is connected to the output of the vertical displacement block 6 of the horizontal scale, a. the second input of the second summing amplifier k is connected to the output of the block 7 for displacing the vertical scale horizontally. The outputs of the generator 8 of sinusoidal and cosine voltage are connected to the inputs of block 9 of changing the levels of sinusoidal and cosine voltage, the output of the sinusoidal signal of the last block is connected to the first input of the third summing amplifier 20, and the output of the cosine wave signal is connected to the first input of the fourth sum amplifier 21. Second the input of the third summing amplifier 20 is connected to the output of the block 15 of the frame of the reference frame vertically, and the second input of the fourth summing its amplifier 21 is connected to the output of m block 16 offset rapper horizontally. The output of the second D / A converter 3 is connected to the input of the voltage divider 4, the input of the measuring voltage generating unit 17 and analog inputs of the sixth 2it and eleventh 31 keys. The analog inputs of the fifth and tenth, 30 keys are connected to the output of the first DAC 12. The analog inputs of the seventh 25 and twelfth 32 keys are connected to the output of a voltage divider. The analog inputs of the eighth 26th and thirteenth 33 keys are connected to the bus 39 z $ zero potential. Analog input

the second key 27 is connected to the output of the third summing amplifier 20, the analog input of the fourth key 3 is connected to the output of the fourth summing amplifier 21; the analog input of the ninth key 28 is connected to the output of the first summing amplifier 13 analog, the fourteenth key 35 is connected to the output of the second summing amplifier 14 ' The control inputs of all the keys 23-36 are connected to the corresponding outputs of the key management unit 18. The outputs of the keys are connected to the input of the summing amplifier 37 vertical deflection, and the outputs of the keys 30-36 are connected to the input of the summing amplifier 38 horizontal deflection. The output of the measuring voltage generation unit 17 is connected to the first output of the measuring element 40 and the first input of the differential amplifier 19. The second output

of the second digital amplifier (1 3, then the sawtooth voltage can be obtained from the output of the latter by changing the symmetrical measuring element 40 to the input of the analyzed object 22 / with the second input of the differential amplifier 19 and the analog input of the third key 36. The output of the differential amplifier 19 is connected to the analog the input of the first key 29. The device operates as follows: 6 clock. The clock pulses from the generator 1 are fed to the input of the reversible double counter 2, which counts in the Account mode from O to, and then in the Account mode from to O and so on. Here, p is the number of bits of the reversible binary counter. In the current device layout, the reversible binary counter 2 is used. Thus, counter 2 counts from O to 1023, and then from 1023 to O and so on. Reverse signal from reverse binary counter 2 is supplied, to the input of the binary counter 10. The latter operates in the V mode with a natural change of states, changing them from 0 to 2 -1, where m is the number of bits of the binary counter 10. The current device layout uses a binary counter. Thus, counter 10 counts from 0 to 103. Above the time diagrams, numerals 41 ,. 42, 43 ,,, .., 10D all counters are marked 10 (FIG. 2). Since the outputs of the bits of the reversible binary counter 2 are connected to digital inputs relative to the ground potential of the tire (steering potential. This voltage is shown, for example, at the beginning of the timing diagram of the signal in Fig. 2. A similar sawtooth voltage is removed from the output of the voltage divider a smaller (e.g. 10-20 times) amplitude. The key management unit 18 is designed to generate control signals for the keys 23 to 26. Consider the implementation of a device that generates a picture on the screen of a CRT (FIG. 3) where 104 is zero coordinate lines passing through the origin of coordinates, 105 are grid lines, Ub is a vertical scale that can be moved horizontally to any place of the grid, 107 is horizontal to a scale that can be moved vertically to any place of the grid, 108 - point , corresponding to the origin of coordinates, 109 - a bright cross point 108 and a cross 109 form the identifier of the origin of coordinates) 110 - the frame, formed in the form of a circle with a variable radius, 111 - observable characteristic, in this case, the input characteristic of the typical TTL element . To distinguish the abscissa and ordinate axes, as well as the scales, their brightness is made twice as large as that of the other grid lines. The brightness of the observed characteristic depends on the duration of the corresponding control pulse (MD) and can vary with respect to the brightness of the other grid lines from 1 to 6. This allows a significant increase in the functional capabilities of the device. To form the painting shown in FIG. 3, the key management unit 18 should generate a sequence of MDs 111-122, the correspondence of which to the keys is clear from FIG. 1. The structure of block 18 can be performed in various ways, for example, in the form of a combinational circuit with six inputs variables, which are the outputs of the bits of the binary counter 10, and with twelve outputs either on a programmable read-only memory (PROM) and so on In the device layout, unit 18 is made on an EPROM of the 155REZ type with 32x8 bit organization. Five address inputs of the 155REZ chip are connected to five younger bits of the binary counter 10, and the high-order output of the latter is connected to the input of the Choice chip 155RE H To implement the sequence of UI 111-121, two bodies of 155REZ are sufficient. Pulse sequence 122 implements

with on the decoder on the structure determined by the desired brightness and the number of observed characteristics. The static characteristic of the object being analyzed can be observed for two states, for example, the input characteristic of element 2I-NOT, when the second input is at level O, or level 1, the output characteristic for state of output or 1 at the output and

Claims (2)

1. Television methods and information display devices. Ed. M.I. Krivosheev. M., Soviet Radio, 1975, p. 66-81. 2. Analysis and calculation of integrated circuits. Ed. D.Liina, C. Meyer, D. Hamilton, Part 2. Trans. from English, M., Mir, 1969, p. 368-375 (prototype). HJ 404o4j- j4jSO "0 04oS, 4j i i H1  Oi ": t 5: St5 §§§§§§§8