SU930681A1 - Multifunctional multi-valued logics circuit - Google Patents

Description

(S) MULTIFUNCTIONAL SCHEME OF MULTIPLE. The invention relates to the field of computer technology and can be used in digital computing devices operating in a non-binary number system using k-valued logic circuits. A known element of k-valued logic based on ECL switches containing input buses, a source of logic levels, an output function generation unit 1. A disadvantage of the known element is that it has relatively narrow functionality, since the output signal is in a given dependence on signals served on the input from the source of logic levels and implements strictly preassigned functions without providing the implementation of other functions of multi-valued logic. A multifunctional logic circuit of multivalued logic is known, containing input buses, a source of logical LOGIC levels, a block of determinants of logical levels, a block of logic level drivers, and an element of the extremal logic level sample, whose information inputs are connected to the outputs of a logic level drivers block, whose information inputs are connected to outputs block of determinants of logic levels, informational inputs of which are connected to input buses, outputs of the source of logic levels dineny with the corresponding inputs of the blocks of determinants, the shaper of the logic levels and the element of the sample of the extremal lo. level 2. A disadvantage of the known device is that the block of logic level drivers only provides direct conversion of one logic levels of input signals to other logic levels, and therefore the known device provides only elementary functions of k-valued logic and does not provide implementation of more complex devices. k-valued logic (for example, k-triggers, k-generators, ditch, etc.). The purpose of the invention is to expand the functionality, namely, to ensure the implementation of more complex devices of k-valued logic (for example, k-triggers, k-generators, etc.), except for devices that implement elementary k-valued functions. This goal is achieved by the fact that a multifunctional multivalued logic circuit containing input buses, a source of logic levels, a block of determinants of logic levels, a block of drivers of logic levels, and an element of the extreme logic level sample, whose information inputs are connected to the outputs of the block of drivers of logical levels, the information inputs of the block of determinants of logic levels are connected to the input buses, the outputs of the source of logic levels are connected to the corresponding inputs of the blocks of the determinants of logic level drivers and an element of the extreme logic level sampling, a block of logic level converters and a block of two-digit logic elements are entered, the outputs and information inputs of which are connected to the information inputs of the logic level drivers block and the logic level converters outputs , informational inputs of which are connected to the outputs of the block of determinants of logical levels, the corresponding outputs of the source of logical levels of Uno with inputs of a block of logic level converters and a block of elements of two-digit logic. In FIG. 1 shows a multifunctional scheme of multi-valued logic; in fig. 2 is a k-flip-flop scheme; in fig. 3 examples of implementations of basic elements; in fig. - implementation of a two-digit logic scheme for providing a k-flip-flop; in fig. 5 is the same for providing the k-generator in FIG. 6; the same for providing the k-generator with a memory; on . 7 the same for providing k-one-shot 14 with a tunable pulse width of each logic level; in fig. 8 - the same, to provide a k-one-shot with one pulse duration of all logic levels; in fig. 9 - multifunctional two-digit logic circuit. The multifunctional multivalued logic circuit contains a block of 1 logic level detectors, input buses 2, a source of 3 logic levels, a block of logic level transducers, a block of 5 two-digit logic elements, a block of 6 logic level drivers, an extremal logic level sample 7, a bus of 8-11 voltages logic levels O, 111 II, respectively, buses 12 and 13 of the bias voltage, information inputs of a block of 5 elements of two-digit logic, outputs 17-19 of a block of 5 elements of two-digit logic, basic elements - 20, block 1 of determinants of logical levels and element 7 of the sampling of an extremal logical level, the basic element 21 of the block k of converters of logical levels, the basic elements of a block of 6 drivers of logical levels. entrances, 2ij and 25 basic elements, output 26 basic elements, inputs 27-30 And output 31 basic elements 21; inputs 32-35 and output 36 of the basic elements, two-digit generator 37, block 38 two-digit logic, two-digit one-shot 39, two-digit logic triggers, elements OR 42, elements NAND and NOT elements, elements NAND and elements OR NOT . Input bus 2 (figure 1) is connected to the information inputs of block 1 of logic level determinants, the outputs of which are connected to information inputs of block 4 of logic level converters, the outputs of which are connected to information inputs of block 5 of two-digit logic elements, the outputs of which are connected to information inputs of block 6 logical level drivers, the outputs of which are connected to the information inputs of element 7 of the sample of extreme logic

level, the source outputs 3 logical levels are connected to the corresponding inputs of blocks 1-6 and element 7

Bus 8 (FIG. 2) is connected to the input of 25 elements, to the inputs of 33 elements, to the first power input of the unit 5 and to the inputs 30 of the elements 21; bus 9 is connected to the input 35 of the element 22-1 and to the input of the element, tire 10 is connected to the inputs 3, 35 and respectively elements, and bus 11 is connected to the input of the element, to the input 35 of the element., to the second power input of the block 5, c the inputs 28 of the elements 21 and with the input 23 of the element, the bus 2 is connected to the inputs of the elements, the outputs .26 of which are connected respectively to the inputs 27 of the elements 21, the outputs 31 of which are connected respectively to the inputs 1L-16 of the block 5; the outputs 17-19 of which are connected to the inputs 32 respectively, the elements of the outputs of the ST which are connected respectively to strokes element input. which is connected to the input element.

The proposed device uses negative coding, i.e. the logical level is defined by e-: with a magnitude of negative voltage. As an example of a specific implementation, FIG. 2 illustrates a multifunctional scheme for four-digit logic.

The device works as follows.

The input of block 1 of logic level determinants receives the input signal via bus 2. In block 1, the input signal is compared with the logic levels of the source of 3 logic losses using basic elements. At the same time, the input signal and the logic level with which it is compared are fed to the inputs and; . If the input bc is coincident with the compared logic level, the output of the base element (s) will be zero, since the input 25 is connected to the bus 8, i.e. with level zero. Otherwise, the output 2b will be a logical level that is different from zero.

Thus, when arriving on bus 2, the non-zero input

signal, but one of the outputs of the 26 elements of block 1 will be a zero level, and on the remaining outputs 26 - logical levels other than zero.

The signals from the outputs of the 26 elements, are fed to the inputs of the 27 elements of the block 21. At the output of 31 elements 21, the maximum (K-1) -th logical level appears when arriving at inputs 27 of zero levels, and when arriving at inputs of 27 logical levels other than zero, at outputs 31 there will be zero logical levels.

Thus, on one of the inputs of block.5 there will be a logic level K-1, and on the others - zero levels. The presence of a logic level K-1 on one of the inputs will correspond to a logic level different from zero on bus 2. When the input signal on bus 2 corresponds to a logic zero, then all inputs will have zero logic levels.

In block 5, when a logical level K-1 arrives at one of its inputs, a necessary two-digit logic function is realized, and one of the outputs 17-19 of unit 5 shows a zero logic level, the remaining outputs will have logic levels K-1.

The signal with output 17-19 of block 5 is fed to the inputs of 32 elements of block 6. The inputs of 33 elements receive a logic zero level, and inputs 35 are supplied with logic levels other than zero.

When entering the input 32 elements. the logic level K-1 appears zero at their outputs 36, and when a zero level arrives at input 32, the output 36 appears at a logic level which enters input 35.

Therefore, if at one of the output / foe 17-19 of block 5 there is a zero level, the output 36 of the corresponding element from 22 1-22 "3 block 6 will have the required logic level and the remaining outputs of block 6 will have zero logic levels.

Claims (2)

The signals from the outputs of the CB elements 22 1-22 3 block 6 is fed to the inputs 23 1-23 "3 elements, which realizes the maximum function when connecting input 2 of element 20 to an arbitrary input in this case with the input of the element, and output 26 of element 20 will be the maximum logical level from the inputs to the inputs, i.e. required logical level. When the bus 2 multifunctional scheme of multi-valued logic / Fig. A - .- „, Y will have a logical level other than zero (for example, 2), then at the corresponding input (input 15 is K-1, the others have zero level. Thus, the corresponding trigger will be tripped (AND 2 a circuit of two-valued logic and through the elements of the OR, the previously overturned trigger (one of,) is reset. Therefore, one of the outputs 17-19 (output 18) shows a zero level removed from the inverse output of the trigger, on the others a logical level IC-1. With further, the zero level from one of the outputs 17-19 (output 18) enters the element f The output of the same logic level as that supplied to the bus 2 of the multifunctional multivalued logic circuit (logic level 2) The remaining outputs (outputs 36 elements and) of block 6 will have zero levels. Thus, at output 26 of the element of the extreme logical level sampling ( In this case, the maximum logical level will be determined by the logical level of the input signal (logical level 2. After the input signal is removed, the output of the multifunctional multivalued logic circuit will not change. When the input signal with a different logic level arrives later, the previous output signal is changed to the same as the input. This level will be memorized by means of a two-digit trigger. In the case of a smoothly varying voltage applied to bus 2, the output element 26 will have an approximate digital a sign of this example, the bridegroom, i.e. The k-digit trigger can be used as an analog-to-digital converter. When at one of the inputs 14-16 block 5 of the two-digit logic is lo 9 a, g y. Level K-1, then from the two-digit rei-fepajpa 37 (fig. 5) through the I-NOT elements are passed to one of the outputs 17 -19 zero-level pulses, which are further converted into pulses with an amplitude of the logic level of the input signal. Thus, when a multifunctional multi-valued logic of an arbitrary non-zero logic level arrives at the output, there will be pulses with an amplitude that logical level. After the input logic level is removed, the output pulses stop and the zero level is set. FIG. Figure 6 shows a two-digit logic circuit for providing a k-digit generator at the output of which the pulses continue to be generated with an amplitude of the logic level of the input signal after it has been removed. The logical level of the amplitude of the generated pulses changes when the input signal arrives with a new, non-zero, logic level. In block 5 of the two-digit logic (Fig. 6), the circuit 38 of the two-digit logic is used to memorize, as shown in Fig. 4. In this case, the inputs of the AND-NOT elements are connected to the corresponding direct inputs of the two-digit triggers. When at one of the inputs 14-16 of block 5 of two-digit logic there is a logic level from a two-digit one-shot one-shot 39 (FIG. 7), one of the elements NOT to one of outputs 17-19 receives a zero-level pulse, which is subsequently converted into a pulse with an amplitude of logic input level. Thus, when a multifunctional multi-valued logic of an arbitrary non-zero logic level arrives at the input of its output, we obtain a pulse with an amplitude of the same logic level. According to this two-digit logic scheme, the duration of the output pulses is rearranged for each logic level separately, as for generating pulses for (the dogological logic level has a two-digit vibrator 33. If it is necessary to generate output pulses of a NOI for a logic level, a two-digit scheme is used logic in accordance with Fig. 8. In this case, a two-digit one-shot 39 is switched on if a logic level K-1 is present on an arbitrary input lA-16, the pulse from which is transmitted through one of the AND-N elements to one of the outputs 17-19 in accordance with the presence of the logic level K-1 on one of the inputs.A Fig. 9 shows a diagram of two-digit logic, the use of which allows to realize arbitrary functions depending on the logic level of the input signal multifunctional multivalued logic circuits. It contains two-valued logic circuits, each of which washes to represent an arbitrary two-digit logic circuit. If there is a multifunctional multivalued logic input input other than zero, one of the inputs will have a maximum logic level K-1 which will trigger one of the two-digit logic circuits at the output of which, after implementing a two-digit function, the level K-1 appears depending on the output connection 0 1 "0 3 circuits, to the elements OR-NOT at one of the outputs 17-19 will be zero level. Thus, by submitting a multi-valued logic specific to the input of a multi-functional logic circuit, we connect a two-digit logic circuit corresponding to this level to work and after this circuit implements a given two-digit logic function depending on the connection of its direct output to one of the OR elements -Do not get at the output of a multifunctional multivalued logic scheme a certain logic level, indicating the end of the implementation of the two-digit function of the connected one of schemes. The output logic level is fed through an additional OR element (not shown in Fig. 1) to the input of a multifunctional multivalued logic circuit and thus switches the second one into operation, after implementing the two-digit function 8110. the OUTPUT logic level, coming through that additional element OR to the input of the multifunctional multivalued logic circuit, connects the third of the circuits, etc. At the same time, the subsequent one of the two-digit logic circuits is reset by the previous working circuit. two-digit logic circuits that can contain actuators to control the necessary elements of objects and their state sensors. Thus, the implementation of a control cycle of technological processes according to a given program is ensured, consisting in the sequence of working out private control cycles of the components of this process, which is realized by appropriate connections of the outputs of two-digit logic circuits with OR-NOT elements. The invention is a multifunctional multi-valued logic circuit containing input buses, a source of logic levels, a block of logic level determinants, logical level drivers, and an extreme logic level sample element, whose information inputs are connected to the outputs of a logic level drivers unit, information inputs of a block of logic level identifiers connecting to input buses, the outputs of the source logic levels are connected to the corresponding inputs of the blocks of determinants, form Logic levels and an element of an extremal logic level, characterized in that, in order to expand its functionality, a block of logic level converters and a block of two-digit logic elements whose outputs and information inputs of which are connected to logic level drivers and with the outputs of the block of logic level converters, the information inputs of which are connected to the outputs of the 11 block of determinants of logic levels, respectively vuyuschie outputs SOURCE ka logiJcheckix levels r inputs are connected to the converter unit g logic levels and two-valued logic block elements. 1 Sources of information taken into account in the examination 1.Radio-Fernschen-Elektronik, 1975, T.Zif, N 12, p. 389-393. 2. USSR author's certificate for application No. 2875002 / 18-21, cl. H 03 K 19/20, 1980 (prototype). .J II Fig, 1  g R J L 29 30 53 5 " G. one I Phi. 3 I „J FIG. five f9 FIG V FIG, € ZP R FIG. 7 R I FI9.L