SU922770A1 - Device for computing mathematical expectation - Google Patents

Description

(54) DEVICE FOR CALCULATING MATHEMATICAL EXPECTATIONS

Claims (2)

, 1 The invention relates to automation and computing and can be used for hardware analysis of processes and statistical processing of data arrays. A smoothing device is known that contains a register, a first adder, two AND elements, an OR element, a sign trigger. This device implements an algorithm according to the recurrent formula SGKH TL - T5 iVA where Xgfn gAh-T respectively} and (1-1) is the value of the signal to be smoothed: Hz is the current I-ta ordinate of the original signal tn. This device has a simpler scheme, however, the estimate of the mathematical expectation, computed by the above algorithm, is not sufficiently efficient, and therefore the device has a low speed. Closest to the proposed technical entity is a digital smoothing device containing the first adder, the first input of which is connected to the output of the shift register, the first input of which is connected to the output of the first adder, the second input of the shift register is connected to the first output of the control unit, the second adder 2. - The disadvantage of the device is the low accuracy of the calculation of the mathematical expectation, since the calculation of the mathematical expectation gives a biased estimate due to the nonoptimality of the implemented operator averaging. This method of calculation is also characterized by the accumulation of errors, which also increases the overall error in the calculation of the expectation. This limits the use of this device in the analysis of random processes. The purpose of the invention is to increase the accuracy of the device. The goal is achieved by the fact that the device for calculating the mathematical expectation contains m + 2 additional shift registers, while the output of the first adder is connected to the first inputs of the t-additional shift registers, the outputs of which are connected to the corresponding inputs of the second adder, the output of which is connected to the first to the input tntl of the additional shift register, the second input of the first adder is connected to the output of the (t + 2) th additional register of shifts, the information inputs of which are combined with the information input 1 and the inputs and the control unit are input devices, a second input of the (m + 2), the additional shift register is connected to the second output control, control outputs of which are connected respectively to the second inputs m additional; shift registers and (m + l) -ro additional shift register. ,; In addition, it differs in that the control block contains the block of the elements OR, the pulse generator, the counter of the number of the selection, the block of setting the division coefficients, the block of comparison, the counter is a group of TP - OR elements, two frequency dividers, a group of (t + 3) AND elements and a group of () flip-flops, with the first inputs () of the AND elements of the group combined and connected to the output of the pulse generator, the second inputs m of the elements AND groups are connected respectively to the single outputs m - triggers of the group, zero inputs of which are “combined with zero input (Mon-1) trigger, with food input (t + 2) -th trigger and connected to the output of the first frequency divider, the input of which is combined with the first inputs of the TP elements of the OR group and the connection output of the (mon-1) -th element of the AND group, the second input (tn +1) -ro of the AND element of the group is connected to the single output (m + t) -ro of the trigger, the single input of which is combined with the input of the count i of the sample and connected to the output of the block of the elements OR, whose inputs are the information inputs of the control unit, the outputs sampling counters are connected to the corresponding inputs of the block specifying the coefficient dividing the output of which is connected to the first inputs of the comparison unit, the second inputs of which are connected to the outputs of the counter, the input of which is connected to the output of (t + 2) -th element of AND group, the second input of (PI-2) -th element of AND group is connected to single output (hp + 2) th trigger of group m outputs of comparison unit connectable) to zero inputs of t-flip-flops groups, outputs of m - elements AND groups are connected to the second inputs of the corresponding elements OR groups, the third inputs of which are combined with the input of the second frequency divider and connected to the exit the y (t + 3) -th element of the I group, the second input of which is connected to the unit output of the (t + 3) th group trigger, the unit input of which is combined with the unit input of the (t + 2) -th group trigger and connected to the k-th the output of the comparator unit, the output of the second frequency divider is connected to the zero input of the (m + 3) -th group trigger, the output of the (m + l) -ro element AND of the group is the first and second outputs of the control unit, respectively, the outputs of the m-elements OR The groups and vni + 3) -ro of the element AND the group are the corresponding control outputs of the control unit. I. . . ,, Fig, 1 shows a block diagram of the device ;; in fig. 2 - control unit block scheme. The device for calculating the expectation contains the first additional wavelength 1 st shift register 1, the second adder 2, t shift registers 3, the shift register 4, the first adder 5, the second additional shift register 6, control block 7. The control unit 6 shown in FIG. 2, contains a block of 8 elements OR, a first trigger 9, a counter 1 o the number of counts, a block 11 defining division factors, a block 12 of comparison, a counter 13, a second element 14, a second trigger 15, a generator 16 pulses, an element 17, a group of m elements And, the third element is And 19, the group of TP triggers, the third trigger 21, the first frequency divider 22, the group m elements OR, the second frequency divider 24. The arithmetic mean value of m x fn random variable X .x, .and where X; - the current i-th ordinate of the original signal, the p-ordinal number of the reference, gives an unbiased estimate of the expectation with the minimum variance in the class of linear estimates. The implementation of an ideal averaging operator (an ideal adder with; rationing by N) I-1G is associated with certain difficulties due to the nature of the computational operations (I). With any pre-set accuracy of calculating the mathematical expectation, the factor 1 / N can be approximated by the sum H / - where a. - takes the value I, if the given amount is included in the total amount, and O, otherwise. The upper limit of the sum is selected from the condition. where is the admissible approximation error, Substituting (.2} in U), we have. -tc.1c) Calculating the expectation from (.3) is performed using simple arithmetic operations of addition (subtraction) and shift, which is very important for the development of specialized information processing devices. The device dp of calculating the mathematical expectation, realizing the expression Sz, works as follows: Samples. The input function X, in the form of a parallel code, is fed to the input buses simultaneously to the information inputs of the shift register 6 and the control inputs of the control unit 7. 8 of the control unit 7, a pulse is generated which cocks the trigger 9 and at the same time increases the content of the counter 10 of the reference number by one. A count number counter 10 controls the division ratio setting unit 11. Each new counter state of 13 counts at the output of block 11 of assignment of coefficients corresponds to a certain combination of code words, the number of which is equal to the number of registers in the group of registers 3 of the shift registers. The first trigger 9 opens the element And 17, through which the pulses from the generator output 16 pulses arrive at the input of the first frequency divider 22, as well as the first and. the second outputs of the element And, 14 control. The conversion factor k of the first frequency divider 22 is equal to the number of bits m of the shift register 4. Thus, from the first and second outputs of the control element AND 14, a series (sequence) of shift pulses is controlled, which shifts the contents of registers 4 and 6. (Assume that shift register 4 contains the result of the previous calculation cycles). From the outputs of registers 4 and 6 of the shift information is fed to the inputs of the adder 5, the results of adding each step (shift) are recorded in the higher bits of registers 4 and 3 of the shift and moving towards the lower ranks of these registers. At the moment of equal number of shift pulses of the conversion factor of the first the divider 22, the latter generates a signal that returns the first trigger 9 to the initial state. The first trigger 9 closes the element. And 17. Registers 4 and 3 of the shift contain the sum of the ordinates of the original signal, i.e. C X, where I is the current count. The signal from the divider 22 frequency is cocked with triggers 15 and, which open the corresponding elements AND 14 (l8 -, - 18). The pulses of the reference frequency through the open elements And and through the elements OR 23 -23 arrive at the outputs of the control unit 7, as well as through the element 14 at the input of the counter 13. The length of the series of shift pulses generated at the outputs of the control unit 7 is specified by the block 11 . nor division factors. At the moment of equality of the current code in the counter 13 with one of the code words of the block P, the assignment of the coefficients to the corresponding output of the block 12: the comparison produces a pulse, which sets one of the triggers 20 to 20 to the initial state. At the same time, the content of the corresponding shift trigger 3 is turned off, i.e. divided by a given factor of 2, where j is the number yes “and the shift pulses for a given register. In registers 3, shifts to the end of sdvnga operations are contained in the following: Bx .... a .... | and NH 5: 1 Impulse, formed on the 10th output of the comparison block 12, sets the triggers 15 and 20-20ff B the initial state, and the third trigger 2 overturns and opens the third element AND 19. The pulse sequence from the generator output 16 pulses through the open third element AND 19 and the OR elements arrive at the outputs of the control unit 7, as well as at the input of the second frequency divider 24. The conversion factor of the second divider 24 is equal to the number of bits of the registers 3 and I shift. Block 7 of the control panel provides a series of shifting pulses to the control inputs of the 3 and 1 shift registers. From the outputs of the registers 3 shifts ga information comes out. to the inputs of the adder 2. The result of the addition is recorded in the higher bits of shift register 1 and is advanced in the direction of the lower bits of this register. By the time the second frequency divider 24 ends, the shift registers 3 are zeroed out, and c. the I shift register will be fixed with the sum of Φ in p. vpi :: x .. jsOUl The last expression naturally coincides with the expression (.3) of the calculation of mathematical analysis 1. The maximum computation time for the current mathematical estimate in cycles is equal to Wc otViH) where is the duration of th 1 offv frequency, n is the number of bits of the 4 rdshift; number of register bits 3 shift. The accuracy of calculating the mathematical expectation in the proposed device (determined by the number of re-shift shears, i.e. the approximation accuracy of 1 / N, where N is the current reference number. For most practical tasks of analyzing random processes, the number of 3-shift registers is quite can be limited to 5, because in this case the error of the mathematical expectation does not exceed 1.0% for any of the readings. The device for calculating the mathematical expectation with a unified parallel-sequential structure has the simplicity c standard digital elements and relatively high homogeneity and regularity, which makes it possible to fully utilize the possibilities of modern integrated technology for implementation in the form of one large IIH circuit.The device for calculating the expectation combines the contradictory requirements of reliability, speed, unification and manufacturability of the structure. This goal is achieved without complicating the number of operations, which is valuable for obtaining current estimates of controlled parameters. Implementing a device for calculating a mathematical expectation provides a great effect compared to existing devices, since the accuracy of calculating mathematical prediction is increased, which expands the scope of this type of device. Claim 1. A device for calculating the expectation that contains the first accumulator, the first input of which is connected to the output of the shift register, whose input is connected to the output of the first adder, the second input of the shift register connected to the first output of the control unit, the second adder, which is different the fact that, in order to improve accuracy, the device contains mon-2 additional 1 shift registers, the output of the first adder is connected to the first inputs m of the additional shift registers, whose outputs are connected with The tCTByra iw inputs of the second adder, the output of which is connected to the first 9th input (m + l) -ro of the additional shift register, the second input of the first adder are connected to the output (): r of the additional shift register, the informational inputs of which are combined with the informational inputs of the control unit and are the inputs of the device, the second input of the (t + 2) -th additional shift register is connected to the second outcome of the control unit, the control outputs of which are connected respectively to the second inputs m of the additional shift registers and (nn-l) -ro will complement ceiling elements shift register. 2. The device according to claim 1, characterized in that, the control unit comprises a block of elements OR a pulse generator, a counter of the number vnH. bork, unit for setting division factors, unit of comparison, counter, group of gp elements OR, two frequency dividers, group of (t + 3) elements I, and group of () triggers, with the first inputs (t + 3) elements and groups are combined and connected to the output of the pulse generator, the second inputs m elements and groups are connected respectively to single outputs m triggers groups, zero inputs of which are combined with zero input (t + 1) -th trigger, with unity) M input (pn-2) th trigger and subdivided to the output of the first divider of the C, the input of which is union of the first inputs of m elements or groups and is connected to the output () -th elements .ta group and the second input (nn-t) -ro AND gate group connected to a single output {m + t) -ro trigger. the unit input of which is combined with the sample counter input / input and connected to the output of an OR block; 25 40 010 whose inputs are the information inputs of the control unit; the outputs of the sample counter are connected to the corresponding inputs of the division ratio setting unit, the outputs of which are connected to the first inputs of the comparison unit, the second inputs of which are connected to the outputs of the counter, whose input is connected to the output of the (ni + 2) -ro element of the AND group, the second input of the (t + 2) -th element of the AND group is connected to the single output of the (t + 2) -th group trigger, t - in the comparison unit moves are connected to the zero inputs of the group m triggers, the outputs of the elements of the AND group are connected to the second inputs of the corresponding TP elements of the OR group, the third inputs of which are combined with the input of the second frequency divider and connected to the output of the (t + 3) -th element of the AND group, the second input of which is connected to the unit output of (mon-3) th group trigger, the unit input of which is combined with the unit input of mon-2 group trigger and connected to the w-oMy output of the comparator unit, the output of the second frequency divider is connected to . the zero input (mon-3) of the group trigger, the output of the (pN-1) -th element of the AND group are the first and second outputs of the control unit respectively, the outputs of the n-elements of the OR group and the {iiH3} -ro element of the AND group are the corresponding controls control unit outputs, Sources of information taken into account during the examination 1. USSR author's certificate No. 356644, cl. B 06 F 15/36, 1970. - 2. USSR author's certificate 9 608166, cl. G 06 F 15/34, 1976 {prototype).  f Phie / H