SU921040A1 - M-phase inverter control device - Google Patents

Description

(54) DEVICE FOR MANAGING SP-PHASE INVERTER

one

This invention relates to an automatic control of the constancy angle of the inverter's stock, in general, the case of n-phase.

A control device is known to be a static inverter, which includes a measuring circuit, a ring counter, from which bits the enable pulses are applied to the valves of the corresponding arm of the converter 1.

The circuit ensures stable operation of the converter and the symmetry of the phases of the triggering pulses in each converter arm, but since the recovery is carried out at the minimum marginal angle of the stock of one phase, the stock angles in the other two phases can reach significant values, which reduces the power factor and degrades the energy performance converter

Of the known devices for controlling the inverter, the closest technically is a device for controlling a pp-phase inverter containing m control channels — one for each phase, each of which contains a comparison unit connected by one input

a switching sensor, another input with a stock angle adjuster, and its positive and negative error inputs with the corresponding input of the phase control unit, and a half-period polarity sensor 2.

A characteristic feature of the operation of this controller is the fact that

10 that the formation of pulses from the valves in each phase is carried out on the basis of the mismatch information in the previous half period, i.e. information on the operating mode of the counter-15 control loop of the converter A significant disadvantage of such a single control is that, with an increase in load, there is a slight difference in phase (within permissible values) over half-periods of control signals for unlocking the valves when the inverter operates with a small angle of reserve (about 20 el. Degrees and less) it is unstable, its operation is unstable, resulting in overturning. Such a phenomenon arises due to a sharp increase in the multiphase character of the generated control signals over half-periods, caused by a mismatch for the given half-period of the error obtained in the other half-period of the voltage. With a significant setpoint of the specified reserve angle, the transient processes in the inverter have a pronounced oscillatory nature, and when the setpoint is lowered, the operation of the controller becomes unstable. As a result of the observed occurrence, in one half-period of the inverter phase, the reserve angle will increase the width, and in the other half, the retention time of the locking properties of the valves operating in this half-period will be reduced. If the process of restoring the locking properties of the valves does not have time to complete by the time of alternating alternating voltage change, then the valves cannot be closed and with a further increase in voltage of another sign, the sum of generator and network imbalances will result in a short circuit called inverter tilting. The goal of power loss is to increase stability and improve the dynamic performance of the inverter. The goal is achieved by the fact that in the device for controlling the inverter the phase control unit contains a clock pulse generator and two pulse shaping units, each of which consists of two AND elements, a reversible counter, and a code information converter into a pulse-phase generator. connected to the first input of each of the elements And and to the first input of each converter of the code information into the phase-pulse, the output of the positive error of the comparison unit with It is connected with the second input of the first element I, and the negative mismatch output with the second input of the second element AND each of the pulse shaping unit, the output of the polarity sensor: half periods connected to the third input of each of the elements forming the pulses directly, and belonging to the second pulse shaping unit through the inverter, the outputs of the first and second elements AND of each of the pulse shaping units are connected respectively to the summing and subtractive inputs of the counter a, the output of which is connected to the second input of the converter information to the α-phase pulse, the third input of which is connected to the half-period polarity sensor in the first node of the pulse shaping indirectly, and in the second through the inverter. With this arrangement of the device, a control pulse with a delay of 180 e is formed at the output of each of the blocks. hail. Such a device structure for controlling the inverter allows for separate half-periods to obtain an off-loop p-adjustment, in which the valves of this circuit of the inverter power circuit are unlocked depending on the error signal obtained from the previous cycle of operation of the same circuit. The drawing shows a structural pattern for controlling the inverter. The stock angle adjuster 1 is connected by its output to the input of the comparison unit 2, to another input of which a pulse arrives at the end of the inverter commutation from the switching sensor 3, the measuring transformer of which is connected to one of the secondary sections of the power transformer 4. Based on the comparison of the phases of two pulses proportional to a given AND actual stock angles of block 2 forms a time difference interval uS, with the sign of the mismatch corresponding to the communication link, (+ g8 or –D.8) to block 5 of the phase control and. The input of block 5 also receives a signal about the polarity of the current half-period from the sensor b of the polarity of half-periods, and the signal corresponds to the level of the logical unit in the positive aoluperiod and the level of the logical zero in the negative half-period. Elements 7-10 are connected by one of their inputs to the generator of 11 cycles of pulses. In the positive half-period, the high total strength from the polarity sensor b is the half-period o.v. at the inputs of elements 7 and 8, and the input of elements 9 and 10 receives a low potential through the inverter 12. At the same time, at the output of element 7, a burst of pulses is formed (modulated signal + g8), which is fed to the summing input of the reversing counter 13. Thus, the code information of the counter 13 is corrected, which is proportional to the phase of the opening angle of the thyristors of the respective transducer arms. In the negative half-period, a high potential at the corresponding input of the element 10 provides for the passage of a burst of pulses from the output of the element 10 to the summed-up input of the reversible counter 14. The counter code 14 is proportional to the phase of the opening angle of the thyristors of the other arm of the converter. Conversion of the code information into the phase pulse is carried out by converters 15 and 1-6 of the code information into phase pulse, which implements a known conversion method. The converter 15 has three inputs. The first is connected to the generator of 11 clock pulses, the second to the output of counter 13, and the third to the output of sensor 6. The converter 16 has similar connections, the only difference is that one of its inputs is connected to sensor b through the inverter 12. The outputs of the blocks 15 and 16 are connected to the inverter 17, and the control pulses are generated by each channel with a delay of 180 e. hail, and alternate operation of each of the inverter arms is carried out strictly in the corresponding half-period of the supply voltage. If the error signal has a negative sign (-e), then the operation of the circuit is similar to the operation with a positive error (-HS, (S) but burst ( the frequency-modulated error signal (db) is now fed to the subtracting input of counter 13 from the output of the element And 8 in the positive half-period, and to the subtracting input of the counter 14 from the output of the element And 9 in the negative half-period. The control of the inverter allows for both half-periods of the voltage, generally in each C-th phase, the contour control of the converter for the constancy of the stock angle depending on the error signal between the target and the actual stock angles obtained from the previous cycle of its circuit of the inverter power circuit. At the same time, a stable inversion mode and high dynamic characteristics of transition processes, especially at small stock angles, allow significantly (up to 25%) to increase the return ivnoy power recovery to the catenary. Formula of the Invention A device for controlling an rh-phase inverter, containing n control channels, one for each phase, each of the rotors contains a comparison unit connected by one input to a switching sensor, another input to an output angle, and its positive and negative error outputs t with the corresponding input of the phase control unit, and the half-period polarity sensor, different. In order to improve the stability and improve the dynamic characteristics of the inverter, the phase control unit contains a clock pulse generator, an inverter and two pulse shaping units, each of which consists of two AND elements, a reversible counter and a code information converter into a phase pulser , while the output of the clock pulse generator is connected to the first input of each of the elements I and to the first output of each converter of the code information into a phase-pulse, the output of the positive The matching unit is connected to the second input of the first element I, and the negative mismatch output is connected to the second input of the second element AND of each of the pulse shaping units, the output of the half-period polarity sensor is connected to the third input of each of the AND elements, directly to the first pulse shaping node, and to the second pulse shaping unit through an inverter, the outputs of the first and second elements And each of the pulse shaping nodes are connected respectively to the summing and subtracting inputs AMK counter vssod which is connected to an input direct BTOIMM eobrazovatel codebook pulse position information, a third input coupled to a sensor polyrnostn half cycles at the first node directly to pulse shaping, and the second - through an inverter. Sources of information taken into account in the examination 1. US patent 3474321, cl. H 02 M 7/04, 1968. 2. Author's certificate of the USSR No. 337070, cl. H 02 R 13/16, 1969.

Claims (1)

The claims 45 A device for controlling an rh-phase inverter, containing a gp of control channels, one for each phase, each of which contains a comparison unit connected by one input to a switching sensor, another input with a reserve angle adjuster, and its outputs positive and negative mismatch with the corresponding the input of the phase control unit, and a half-cycle polarity sensor, characterized in that, in order to increase stability and improve the dynamic characteristics of the inverter, the phase control unit contains a clock pulse generator, an inverter and two pulse shaping units, each of which consists of two AND elements, a reversible counter® and a phase-to-pulse code information converter, while the output of the clock generator is connected to the first input of each of the AND elements and to the first input of each converter code information into the phase-pulse, the output of the positive mismatch of the comparison unit is connected to the second input of the first element And, and the output of the negative mismatch is with the second input of the second element And of each of the pulse shaping nodes, the output of the polarity half-cycle polarity sensor is connected to the third input of each of the And elements related to the first pulse shaping node directly, and to the second pulse shaping node - through the inverter, the outputs of the first and second elements And each of the shaping nodes pulses are connected respectively to the summing and subtracting inputs of the counter, the output of which is connected to the second input of the code information converter into a phaeoimpulse, the third input of which is connected to the sensor m polarity of the half-cycles in the first node of the pulse formation directly, and in the second through the inverter.