SU1661936A1 - Method for controlling inverter - Google Patents

Abstract

The invention relates to electrical engineering. The purpose of the invention is to improve the quality of the inverter output current by tracking the average load current, the ability to control the first harmonic of the current, the load to zero, limit the maximum values of the load current, and synchronize the clock frequencies of the inverter output phases. For this, the pulses for turning on the inverter keys are produced at the moments of approaching an integrated difference signal (signals of the master oscillator 1 and current sensor), with a positive modulating signal at the moments of approach from below, and negative at approaching it from above to zero. In the inverter control system with this method, an additional integrator 3 is introduced, which is connected with its output to two more comparators 6, 7, and the outputs of these comparators are connected to the keys 30–33 of the inverter. 5 il.

Description

The invention relates to electrical engineering, in particular to converter equipment, and can be used in adjustable AC electric drives.

The purpose of the invention is to improve the quality of the output current of the inverter.

Fig. 1 shows a block diagram of a voltage inverter control device implementing the method; Fig. 2 is a power circuit of a voltage inverter; ha fig. 3 - current and voltage plots in the power circuit and voltage inverter control system; Fig. 4 is a diagram of a polarity determination unit that generates pulses in duration corresponding to the duration of the load current flow at which the ripple current does not touch the zero line; Fig. 5 shows the diagrams of currents and voltages explaining the principle of operation of this unit.

The device contains a modulating signal generator 1 (in this case, a three-phase modulating signal generator — GMS) connected to the subtractive unit 2 by the first output, the output of the inverter power circuit is connected to the second input, the output of the subtractive node 2 is connected to the integrator 3 and the comparators 4 and 5 , the second inputs of which are connected to the second outputs of the HMS 1. The output of the integrator 3 is connected with comparators 6 and 7, to the second input of which the threshold voltage Un 0 is applied. The outputs of the comparators 4-7 through triggers 8 and 9, polarity determination unit 10 , uh ementy 11 and NOT 12, AND gates 13 and 14, flip-flop 15, AND gates 16-25 and OR elements 26-29 associated with power keys 30-33.

The voltage inverter (Fig. 2) includes switches 30-33 performed on the thyristors with full control, reverse current valves 34-37, load phase 38, load current sensor 39. The dashed block 40 represents a single phase inverter. The other two phases 41 and 42 are similar.

The device works as follows.

The voltage across the load is generated by the pulse-width modulation method (Fig. 3b). When forming a positive impulse on the load, the keys 30 and 33 or the diodes 34 and 37 are turned on. Negative impulses on the load are formed by switching on the keys 31 and 32 or the diodes 35 and 36.

A zero voltage at the load at a positive half-wave of the load current is formed by turning on the valve 30 and the diode 36, and at a negative, respectively the valve 31 and the diode 37.

In the areas near the current zero crossing, when the load current is of the same sign, two-pole pulse-width modulation is performed. At current

loads with only one sign, the voltage is generated by the unipolar pulse width modulation method.

Baseband Generator 1

0 (FIG. 2) generates a signal a, which determines the shape of the output current. Fig. 3a shows, as an example, a sinusoidal signal for controlling one phase of the inverter, for which the principle of the system operation is considered.

The other two phases work in the same way,

In node 2 (Fig. 1), the modulating signal 3 is subtracted from the feedback signal proportional to the load current n. Difference signal ig. (Fig. 3d) goes to Comparators 4 and 5 (Fig. 1) and is compared with threshold levels ini and in2, which come from block 1. Threshold levels are 5 each of which are voltage, but have

constant amplitude and do not change when

change in magnitude 3. At the moment of equality

is threshold value 1П1 triggers comparator 4 and the pulse from its output translates

0 the trigger 8 is in such a state that the control voltage is removed from the switch 30, and, conversely, transfers the trigger 9 to the state in which the control voltage comes from the output of the trigger 9

5 to turn on the key 31. The pulses from the output of the flip-flops 8 and 9 are shown in FIG.

The second inputs of the trigger 8 and 9 receive impulses from the –comparators 6 and 7, the input of which receives the integrated

0 by integrator 3 (Fig. 3g), the voltage lЈ. Moreover, the comparator 6 generates a pulse when the integrated voltage approaches the zero level from above, and the comparator 7 produces a pulse when the integrated voltage approaches the zero level from the bottom.

Comparator 5 is triggered at times when the voltage it reaches the threshold n2. This is information about the necessity of changing the polarity of the voltage pulses on the load. The pulses from the comparator 5, the passage through the elements And 13 and 14, control the trigger 15, the pulses from the output of which Uf and L) (FIG. Ground) control

5 elements 16-22 and 24 coincidences, through which the pulses from the triggers 8 and 9 arrive at the corresponding inverter keys. The second inputs of the elements 13 and 14 are controlled by the voltage UQ + - and Uo- (FIG. 3), produced by the unit 1. Positive

the impulse Uo + corresponds to a positive half-wave, and a negative Uo- negative.

Unit 10 generates pulses corresponding in time to the load current, when it has one sign within the clock cycle.

According to FIG. 3, the load current, starting with the moments t2 and up to t4 (FIG. 3H), does not touch the zero axis and flows in the positive direction, but starting with ts and up to t; only in the negative direction. The task of unit 10 is to generate pulses that separate these time intervals (Figures 4 and 5).

Consider the selection of an interval, i.e. the time when the load current flows in the positive direction. The comparator 43 produces pulses (fig. 1) corresponding to the moments of negative values of the current with a positive half-wavelength is. The front edge of this pulse triggers a one-shot 44, which gives a pulse (Fig. 56), equal in duration to a certain minimum current interval in the negative direction. At the same time, it is pulsed (Fig. 5a) and is fed to the trailing edge extraction unit 45 (AECD), and a pulse is generated corresponding to the trailing edge (Fig. Bb). The pulses (fig. 5b, c) arrive at the coincidence element 46, and a pulse is produced (fig. Bg), which in time corresponds to the last intersection of the load current of the zero line. This pulse triggers a trigger 47, at the output of which a pulse Uo appears, triggers the trigger at the moment when the load current again touches the zero line.

With a negative current half-wave "3, elements 48-52 work similarly (figure 4). There is a comparator 48, similar to the comparator 42, which responds only to positive values of the load current, the one-vibrator 49, the falling edge separation unit 50, the coincidence element 51, the trigger 52, the output of which is the voltage Do.

FIG. 3c, o, p represents control pulses, respectively, of keys 30–33, which are produced in such a sequence as to implement the method of controlling an inverter by forming a voltage curve shown in FIG. 3b. The period of formation of the inverter output current curve can be divided into time intervals, shown in FIG.

The control pulses of the key 30 are generated as follows. In the time interval ti-t2, the pulses from the output of element 17 appear as a result of the coincidence of the voltages Ug.U, Uo; in the time interval ta-ta, the pulses from the output of elements 17 and 16 appear when the voltages Ua.U.Uo coincide; in the time interval, the pulses from the output of element 18 when the voltage Ug.U coincides, inverted by Uo.

The control key pulses 31 appear on the time interval tq-ts from the output of element 20 when Ua, U, Uo7Ha coincides with the time interval ts-te from the output of element 20 and 21 when Ug, U, Uo coincides, on the time interval te-t . ti-ta -, from the output of element 22 when Us.U coincides, inverted by Uo.

The key control pulses 32 appear on the time interval from the output of element 22 when Ue.U coincides, inverted by Uo, and on the time interval ti-t2 from the output of element 23 when Ue.Uo coincides, inverted by Uo.

The key control pulses 33 appear on the time interval from the output of the element 24 when Ug, U coincides, inverted by Uo; on the time interval - from the output of the element 25 with the coincidence Ug.Uo, inverted Uo.

Changing the threshold levels 1P1 and P2 to zero when the load current passes through zero leads to the fact that the formation of current pulsations occurs from zero values or close to them.

This ensures that the frequencies of high-frequency pulses are identical across all phases of the inverter, since the inevitable small asymmetry of control channels of different phases does not accumulate from half-period to half-period. As a result, low frequency beats of the engine torque are avoided. By turning on the inverter keys at the moments of approaching an integrated (using an additionally inserted integrator) difference signal with a positive modulating signal from below, and at a negative signal - at the moments of approach of the integrated signal from above to zero, the average value per output current clock is monitored.

It is possible to regulate the first harmonic of the load current to zero, since at 13 0 in the phases of the load, only the alternating ripple of the load current with the average value per cycle and half period equal to zero is known, since the voltage on the load is the same as at double-pole PWM . It also improves the quality of the output current of the inverter.

Claims (1)

Invention Formula A method of controlling a voltage inverter, which consists in forming and applying control pulses to turn on and off the power switches in a given interval of the output current period according to the selected law of pulse-width modulation (PWM) at the moments of equality of the difference voltage of the modulating signal and a signal proportional to the output current, two threshold levels, having the form of a modulating signal with an unregulated amplitude, the first threshold level coinciding in phase with the modulating signal, and the second finding ITS in antiphase, characterized in that, in order to improve the quality of the output current, wherein said raznost-, 0 five 0 my voltage is integrated, the value of the second threshold level is made equal to zero, and the pulses to turn off the inverter power switches are generated with a positive modeling signal at the time of the integrated differential voltage approach, from the bottom, and at a negative time from the integrated threshold voltage approach to the second threshold level, and the specified interval is divided into subintervals, corresponding to a load current and a different current, which is unipolar within the cycle, and form a control pulse power switches on and off according to the law in a uni-polar PWM subintervals unipolar current, and by the law dvuhpol molecular PWM subintervals Hetero-polar current. eleven "one X FIG. j Wt FIG. four