SU919148A1 - Device for adaptive reception of frequency-shift keying signals - Google Patents

Description

one

The invention relates to telegraphy.

A device for adaptive reception of frequency telegraphy signals is known, comprising an analogue-1 No. | flux converter, the outputs of which are connected to the corresponding inputs of frequency dividers, one inputs of which are connected to the output of the reference pulse generator, as well as counters, registers, the first decoder and signal analyzer 1.

However, in the known device, the reliability of reception is insufficient.

The purpose of the invention is to increase the reliability of reception.

To achieve the goal, the device for adaptive reception of frequency telegraphy signals containing an analog-digital converter, KOTopoio outputs are connected to the corresponding inputs of frequency dividers, one of which inputs are connected to the output of the reference pulse generator, as well as counters, registers, the first decoder and signal analyzer, are entered triggers, elements AND, elements OR, a delay element and a second decoder, the outputs of which are connected to

the first inputs of registers whose outputs are connected to the inputs of the first decoder, whose outputs are connected to one input of the signal analyzer, another input connected to the input of the delay element, to the output of the first OR element, to the other inputs of the frequency dividers and to the first input of the first counter, the output which is connected to the first input of the first trigger, the output of which is connected to the first input of the second decoder, the second input of which is connected to the first input of the first element X, the output of the second trigger, the first input of which It is connected to the output of the second counter, to the first input of the first OR element, and to the first input of the third counter, the output of which is connected to the second input of the first OR element, to the first input of the second counter, and to the first input of the third trigger, the second input of which is connected to the second input of the first trigger, with the second input of the second trigger and the output of the second element OR, the first input of which is connected to the output of the second element And, the first input of which 39 is connected to the output of the third trigger and to the third input of the second decoder, with The output of one frequency divider is connected to the second input of the first counter, the output of the other frequency divider is connected to the second input of the second counter and to the second input of the first element AND, the output of which is connected to the second input of the second element OR, the second input of the third counter is connected to the second input of the second element And, and the output of the delay element is connected to the second inputs of the registers. The drawing shows the structural electrical circuit of the proposed device. , The device is a reference generator of 1 pulses, deligels 2. and 3 frequencies, an analog-to-digital converter (ADC) 4, counters 5-7, elements OR 8 and 9, triggers 10-12, elements AND 13 and 14, element 15 delays, decoders 16 and 17, registers 18-20, signal analyzer 21. The device works as follows. The frequency modulated signal fc passed through the driver (not shown) comes in the form of square pulses, the duration and frequency of which are determined by the characteristics of the channel-forming equipment at the transmitting end and the state of the communication channel, to the input of the counter 5. 6 and 7, pulses are received, respectively, from the outputs of dividers 2 and 3, connected by their inputs to the output of the reference pulse generator 1, and the division factors of which are determined by parallel codes, respectively, into the first and second x 4. ADC output value of said codes determined k) are, in turn, an analog signal parameter from the input of the ADC 4 and characterizing the signal / noise ratio in the communication channel. Thus, pulses with a frequency fmin are input to the input of counter 6, and pulses with a frequency f are received at the input of counter 7, the values of fmin and ffnax depending on the signal-to-noise ratio in the communication channel and satisfying the condition

- fcp fmax

mm

where fcp is the known average frequency of the frequency-modulated telegraph signal. The volume of counters 5-7 is selected so that their overflow occurs several times (e less than three) in the interval of the elementary sending of the telegraph signal.

Before the operation of the device, all nodes containing memory elements (triggers) are nullified, and for dividers 2 and 3, the corresponding division factors are defined, determined by the codes on the outputs of the A / D converter 4.

The pulse from the output of the element OR 8 coming through the element 15 of the delay at the inputs

The shift registers 18-20, rewrites the information from the corresponding outputs of the decoder 16 in their first bits, shift the information available in them towards the higher bits. The next pulse at the input of the counter 6 passes through the element 14, open at the first input, the element OR 9, and sets the triggers 11 and 12 to the zero state. 8 Consider three possible cases of filling counters 5-7. 1. fc fmax- In this case, counter 5 overflows first. The impulse from its output sets the trigger 10 into one state, zeroes the counter 6 and, having passed through the element OR 8, zeroes the counter 7 and enters the input Setting the initial state of dividers 2 and 3, setting the new division factors determined by the signal / noise at the moment. Thus, the first input of the decoder 16 is set to 1, and the remaining two inputs is 04. This state of the inputs of the decoder 16 is decrypted by it so that its first output is set to G, and the other two to O. The impulse arriving at the inputs The shift of three-bit registers 18-20 from the output of the element OR 8 through the delay element 15 in which it is delayed by the time t Tnm4 L rewrites 1 and O, respectively, in their first bits. The next pulse at the input of counter 5 passes through the element 13, open on the second input, and the element OR 9 on in The second inputs of the triggers 10–12, set the trigger 10. After that, the a1 counts the pulses of frequency f on the next slice of the elementary parcel. 2. fc In this case, the first overflow counter 7 and the pulse from its output sets the trigger 12 in one state. The second overflows counter 6 and the pulse from its output sets trigger 11 to one state and zeroes counter 5. This same pulse, passed through the element OR 8, zeroes counter 7 and sets the new division factors of dividers 2 and 3. In this case On the first input of the decoder 16, O is set, and on the second and third inputs is 1. This combination of signals on the inputs of the decoder 16 is decrypted in such a way that O is installed on the first and third outputs, and on the second

3- min f s gpa In this case, the first counter overflows 7, the second counter 5, and the third counter 6. Moreover, the situation is possible when the counter 5 overflows simultaneously with the counter 6 or counter 7, Therefore, the following signal combinations are possible at the inputs of the decoder 16 : on the first and third inputs 1, on the second O (- (p with W or 1 (fmin - with tac)) - combinations of signals are decrypted by decoder 16 in such a way that O is installed on its first and second outputs, and on the third 1. The information from the outputs of the decoder 16 is rewritten into the corresponding registers 18 -20 in the manner described above: Triggers 10-12 are null by the following pulse at the input of counter 5 or counter 6, which passes respectively through element AND 13 or element AND 14, element OR 9 to the second inputs of these triggers.

After analyzing the (i + l) -ro portion of the elementary parcel, in the three-digit registers 18 and 19 there is information about the polarity (iH) -ro, i-ro, (il) -ro, and in the three-bit register 20 as reception of these sites. Since the output of each bit of these registers is connected to the corresponding input of the decoder 17, the combination of signals - at these inputs at each moment of time determines the polarity and pumps the reception of the i-th elementary parcel, taking into account the pre- and post-history, i.e. taking into account the polarity and quality of reception. both the i-ro site itself, and (i-1) -th and (i + 1) -th sites.

depending on the combination of signals present at the inputs of the decoder 17 and characterizing the preliminary decision on the polarity and quality of reception (i-1, i-ro, (i + 1) -th plots, signals on its outputs, characterizing the final decision about The polarities and reception quality of the i-ro portion are as follows: if the release or pressing signals are confidently received, 1 correspondingly formed on the first or second output on the third output, in this case, O is formed with an uncertain reception of the elementary parcel on the first and second deshi outputs Rathore About 17 is formed, and on its third output - 1.

The algorithms for making the final decision on the polarity and quality of reception of the i-ro portion of the elementary parcel, taking into account the pre-history, implemented by the decoder 17, may be different.

The signals from the outputs of the decoder 17 are entered into the analysis block 21 at the moment of arrival of the pulse from the output of the element OR 8 to the recording input of this block, in which

the algorithm analyzes the field p1gosg and the quality of reception of all or in a certain way selected areas in the elementary parcel interval, the boundaries of which are {{) {\} eaten by sync pulses (SI) received from a phase adjustment device (not shown), and decides about the capacity and quality of the whole elementary parcel. The release and press signals are removed respectively from the first and second outputs of block 21a, and the signal is erased from the third output of this block.

Thus, the decision on the polarity and quality of reception of the elementary telegraph signal is made not only on the basis of an analysis of the average frequency of the received signal in the interval of this parcel, but also taking into account the law of variation of this frequency in the interval of the parcel.

Claims (1)

Invention Formula A device for adaptive reception of frequency telegraphy signals, containing an analog-to-digital converter, the outputs of which are connected to the corresponding inputs of a frequency dividers, some of the inputs of which are connected to the output of a reference pulse generator, as well as counters, registers, the first decoder and signal analyzer, characterized in that in order to increase the reliability of reception, triggers, AND elements, OR elements, a delay element and a second decoder, whose outputs are connected to the first inputs of registers whose outputs are connected to the inputs of the first decoder, the outputs of which are connected to one input of the signal analyzer, the other input of which is connected to the input of the delay element, to the output of the first OR element, to other inputs of the frequency dividers and to the first input of the first counter, the output of which is connected to the first input of the first trigger The output of which is connected to the first input of the second decoder, the second input of which is connected to the first input of the first element And and to the output of the second trigger whose first input is connected to the output of the second counter, with n with the first input of the third counter, the output of which is connected to the second input of the first OR element, with the first input of the second counter and the first input of the third trigger, the second input of which is connected to the second input of the first trigger, and with the output of the second OR element, the first input of which is connected to the output of the second element I, the first input of which is connected to the output of the third triple and to the third input of the second decoder, and the output of one frequency tel is connected to the second the first input of the first counter, the output of another frequency divider is connected to the second input of the second counter and the second, the input of the first AND element, the output of which is connected to the second input of the second OR element, the second input of the third counter is connected with the second input of the second element And, and the output of the delay element is connected to the second inputs of the registers. Sources of information taken into account in the examination 1. Mashbits L. Sh. Digital signal processing in radio-telephony communication, M., Sv, 1974, p. 53-63 (prototype).