SU896659A1 - Pupil examining device - Google Patents

Description

I

The invention relates to automation and computer engineering, in particular to technical learning difficulties, and can be used for programmed control of students' knowledge.

A device is known that contains elements of the memory and answers of students, reference answers, student learning consoles, a unit of teacher Cl.

This device has limited didactic characteristics and low accuracy of knowledge control.

It is also known a device that contains a response input box connected to a comparison node, a memory unit, a generator, a distributor, a switchboard, a presentation board, and an l2l scoreboard.

The specified device has a low accuracy of knowledge control, limited didactic characteristics.

Closest to the present invention is a device containing memory elements of answers of students and reference answers, comparison circuits, counters

the number of input answers and reference standard, trigger poll Gz.

The device makes it possible to increase the accuracy of knowledge control, but it has limited didactic capabilities .11el of the invention is to enhance the didactic capabilities of the device by recognizing a meaningful response by the device, regardless of

10 forms of his presentation.

The goal is achieved by the fact that in a device containing sequentially included response input block, the first element OR, the first counter,

15, the first switch, the memory block, the input of which is connected to the second output of the response input block, and the output to the second input of the first switch, the trigger and the comparison block, are entered, in the second,

M is the third, fourth and fifth counters, the second, the third and fourth elements are OR, three registers, a decoder, four blocks of AND elements, the second switchboard. 3 four elements And, inverter and element. delay, the output of which through the first element AND is connected to the first inputs of the second, third and fourth elements AND, the input directly from the output of the comparison unit connected through the second element OR to the first input of the second counter, the second input of the first OR element, the first input of the trigger, the first input of the third counter and the input of the inverter, the output of which is connected to the second input of the first element I, the inputs of the registers are the inputs of the device, the output of the first register is connected to the first inputs of the first and second blocks of elements in the AND and the fourth counter, the second input of which is connected to the output of the third element OR, and the output to the first inputs of the second switch and the third block of elements AND, the second input of which is connected to the output of the second register, and the output to the first input of the comparison unit, the second input which is connected via the decoder to the output of the first switch, the first input of the third element OR is connected to the first output of the response input block, and the second input is connected to the output of the second AND element connected to the second input of the second counter, the output of which is connected to second input vtorogs | block of elements I, whose WB1 is connected to the second input of the third element I, the first and second outputs of the trigger are connected to the second inputs of the second and fourth elements I and the second input to the output of the fourth block of elements I connected to the input of the fifth counter and the second input of the third the counter, the output of which is connected to the first input of the fourth block of elements I, the second input of which is connected to the output of the second commutator, the second input of which is connected to the output of the third register, the output of the fifth counter is connected It is connected to the second input of the first block of AND elements, the output of which is the first output of the device; the first and second inputs of the fourth OR element are connected to the outputs of the third and fourth AND elements, respectively, and the output to the second output of the device. The drawing shows a diagram of a device for monitoring students' knowledge. The device contains an input unit 1, connected directly to the response memory block 2 of students and through the OR 3 element with a counter 4 9 the number of response elements, the outputs of which and the outputs of block 2 are connected to the switch 5, the register 6 the number of groups, the register 7 the number of elements in the group, the register 8 of the group code of each response element, whose inputs are the inputs 9 of the device, the inputs of the register 8 through the block 10 elements AND are connected to the comparison unit 11, the other inputs to oh through the decoder 12 are connected to the switch 5. The outputs of the block 11 through the element OR 13 are connected with the counter 14 matched elements, the zero input of the trigger 15, the element OR 3, the counter 16 unmatched groups and the inverter 17. The output of the inverter 17 and the output of the element 18 delay connected to the outputs of block 11 are connected to the element AND 19 connected to the first inputs of the elements 20-22, the second input of the element 22 and is connected to the inverse input of the trigger 15, the direct input of which is connected to the second input of the element 21, the output is connected with the counting input of the counter 16 and the input ohm of the element OR 23. The element OR 23 is connected by the second input to block 1, and the output to the counter of 24 groups of elements, the output connected to the block 1O and the switch 25, the other input connected to the register 7, and the output to the block 26 elements AND, The block 26 is connected to the output of the counter 14, and the output to the single input of the trigger 15, the counter 14 and the counter of the 27 matched groups. The outputs of the counter 27 and register 6 are connected via a block of 28 elements And to the output 29 of the device, B1; || giving a signal The correct answer. In addition, the register 6 is connected to the counter 24 and the block of 30 elements And, the input of which is connected to the counter 16, and the output is connected to the second input of the element AND 20. The outputs of the elements 20 And 20 are connected to the element OR 31, the output of which is 32 devices generating an Error signal. The constructed answer to the question can be represented as: lw, ... m2.) VCw ... lmp) v ... tmg4-l -.w) where t- (ie1i t) are the elements of the answer (words, signs, letters , numbers),. combined by brackets into groups; the operation L means that the elements can take any place in the group;

Operation Y means that the group can take any place in the response.

In order to analyze the correctness of the answer, which can be represented as (1), it is necessary to have information about the element belonging to the group, the number of elements in the group and the number of groups that is entered from the teacher’s console (not shown) on the corresponding tires 9 into registers 8 , 7 and 6. Moreover, for each element of the used alphabet of characters in register 8, the corresponding cell is assigned to which the number of the group to which the element currently belongs is entered. In register 7, for each group of elements, a cell is assigned, in which the number of elements is written. The number recorded, for example, in the first cell must match the number of cells in register 8, in which 1 is written, i.e. number of conditions of the 1st group.

The device works as follows.

From unit 1, the student enters successively the codes of the response elements in the memory elements of block 2, each element in the next cell. After the input of the response from block 1 is completed, a ready signal is received (via which the control of the correct response begins) through the elements OR 3 and 23 to counters 4 and 24. According to this signal 1 is written to counters 4 and 24, and elements whose group number coincides with that recorded on the counter 24. At the same time, through the switch 5, controlled by counter 4, the decoder 12 receives the code of the element recorded in the memory elements of block 2 first. This code is decoded by decoder 12 and fed to the second inputs of block 11. If the direction from decoder 12 coincides with at least one of the directions from block 10, then the group containing this element is found. The coincidence signal from block 11 through the element OR 13 enters the counter 14, cocks the trigger 15, resets the counter 16, and how countable through the element OR 3 enters the counter 4, which provides a connection to the decoder 12 of the next response element. In this case, if the contents of the counter 14 are not equal to the number in the register cell 7 (condition analysis is provided by block 26 and switch 25), then the operation is repeated. If a mismatch is detected, then the AND 22 element opened by the trigger 15 and the output 32 (via the OR element 31) receives a signal

The error means that in this Response Group the content of the elements differs from the standard. If the number of matched elements at the next signal coincides with block 11 is equal to the number

elements in this group, recorded in the corresponding $ 1 register register 7 arriving at the input of block 26 through the switch 25, then a signal is removed from the output of block 26, the translation 5SH1 trigger

15 in the initial state, resetting the counters 14 and arriving at the counting input of the counter 27. If all the elements in all groups coincide, the contents of the counter 27 are equal to the contents of the register

6, which is fixed by Zeus 28, from whose output to the output 29 of the device receives a signal The correct answer.

If at the moment of analysis of the next element of the response, block 11 is removed

If there is a mismatch through elements 17 and 18 in the initial state of the trigger 15, then a single signal arrives at the input of the counters 24 and 16. In this case, the response element is analyzed for presence in the next group until a match is found or at the counter 16 a number equal to the contents of register 6 is accumulated, which is fixed by the DA block and means that the element being analyzed is not in the composition of the standard.

The error signal at the next mismatch through the elements AND 20, OR 31 enters the output 32 of the device as an error signal. .

If during the analysis the element coincides with the reference elements of the group, then this signal from block 11 is fed to the counting input of scheduling 4 and resets to the initial state 16. The device repeats the operations described above.

Device-Gao also allows you to analyze responses like

tfl L ttl (L ... L W

where each element m is recognized as a group of one element.

If the scheme analyzes a selective response, i.e., one element m from a number of proposed students, then the reference code (m) is contained in the first group, in which only one. element.

Claims (1)

The device can also control the effective response, which for its reliability can be represented as (O ;, V rr) V v (a ,, d) V ...,), where a ,, are the numbers in the answer, a brackets mean the union in arbitrary groups of numbers effective response. The device allows you to control the response presented in a freely constructed form, which expands the didactic capabilities of the device, and Namely presents the learner with the ability to form a response in essence without limiting it to the form of the response. The device also makes it possible to increase the objectivity and reliability of the knowledge control by recognizing information presented in a form close to natural, which eliminates the need to control syntax errors that are not related to the content of the answer. Claims An appliance for controlling a student’s knowledge, comprising a sequentially connected response input unit, a first OR element, a first counter and a first switch, a memory block whose input is connected to the second output of the answer input block, and an output to the second input of the first switch, trigger and Comparison unit, characterized in that, in order to expand the didactic capabilities of the device, it contains second, third, fourth and fifth counters, second, third and fourth elements OR, three registers, a decoder, four blocks AND elements, the second switch, four AND elements, an inverter and a delay element, the output of which through the first element AND is connected to the first inputs of the second, third and fourth elements AND, the input directly with the output of the comparison unit connected through the second element OR to the first input the second counter, the second input of the first element OR, the first input of the trigger, the first input of the third counter and the input of the inverter, the output of which is connected to the second input9 the HOME of the first element AND, the inputs of the registers are the inputs of the device, the output of the first go register connected with. the first inputs of the first and second blocks of the And elements and the fourth counter, the second input of which is connected to the output of the third element OR, and the output to the first inputs of the second switch and the third block of elements And the second input of which is connected to the output of the second register the input of the comparison unit, the second input of which is connected via the decoder to the output of the first switch, the first input of the third OR element is connected to the first output of the response input block, and the second input is connected to the output of the second AND element connected to the second the input of the second counter, the output of which is connected to the second input of the second block of elements And, the output of which is connected to the second input of the third element And, the first and second outputs of the trigger are connected to the second inputs of the second and fourth elements And respectively, and the second input - with the output of the fourth block of elements And connected to the input of the fifth counter and the second input of the third counter, the output of which is connected to the first input of the fourth block of elements And, the second input of which is connected to the output of the second switch, the second input The first is connected to the output of the third register, the output of the fifth counter is connected to the second input of the first block of elements AND whose output is the first output of the device, the first and second inputs of the fourth element OR are connected to the outputs of the third and fourth elements AND, respectively, and the output to the second device output. Sources of information taken into account during the examination 1, Author's certificate of the USSR N9 402902, cl. q 01 B 7/02, 1973. 2, USSR Copyright Certificate No. 456294, cl. Q 09 B 7/00, 1975. 3, USSR Copyright Certificate No. 613361, cl. G 09 B 7/02, 1978 (prototype).