SU888209A1

SU888209A1 - Analogue storage device

Info

Publication number: SU888209A1
Application number: SU802900024A
Authority: SU
Inventors: Виктор Васильевич Старин; Владимир Васильевич Захаров
Original assignee: Предприятие П/Я Г-4406
Priority date: 1980-03-24
Filing date: 1980-03-24
Publication date: 1981-12-07

Description

Союз Советских Социалистических РеспубликUnion of Soviet Socialist Republics

Государственный комитетState Committee

СССР по делам изобретений и открытийUSSR for inventions and discoveries

О П И С А Н И Е ИЗОБРЕТЕНИЯSUMMARY OF THE INVENTION

К АВТОРСКОМУ СВИДЕТЕЛЬСТВУ (61) Дополнительное к авт. свид-ву(22)Заявлено 24j03.80 (21) 2900024/18-24 с присоединением заявки № (23)Приоритет Опубликовано 07.12.81. Бюллетень №45TO AUTHOR'S CERTIFICATE (61) Additional to author. certificate-wu (22) Declared 24j03.80 (21) 2900024 / 18-24 with the addition of application No. (23) Priority Published on 07.12.81. Bulletin No. 45

Дата опубликования описания 07.12.81 (11)888209 (51 >М. Кл?Date of publication of the description 07.12.81 (11) 888209 (51> M.C.?

G 11 С 27/00 (ЗЗ)УДК 681.327.G 11 C 27/00 (ЗЗ) UDC 681.327.

.66(088.8).66 (088.8)

Изобретение относится у аналоговой технике, в частности к аналоговым запоминающим устройствам, и может быть использовано для запоминания и воспроизведения частоты сигналов в радиотехнических устройствах с частот-⁵ным выходом информации для последующей их аналоговой обработки.The invention relates to analogue technology, in particular to analogue storage devices, and can be used for storing and reproducing the frequency of signals in radio devices with a frequency- ⁵ output of information for subsequent analog processing.

Известно запоминающее устройство fl] , информация о частоте в котором представлена в виде двоичного числа.A memory device fl] is known, the frequency information of which is represented as a binary number.

Наиболее близким решением по технической сущности и достигаемому результату к изобретению является аналоговое запоминающее устройст-. во [2], в котором за калиброванное время счета импульсы, сформированные из радиосигнала, периодически запол- ₂₀няют двоичный счетчик и сбрасываются. За время счета в счетчике набирается число, которое является мерой входной частоты.The closest solution in technical essence and the achieved result to the invention is an analog storage device. in [2], wherein the calibrated time for counting pulses generated from a radio signal, are periodically filled nyayut binary counter ₂₀ and reset. During the counting period, a number is dialed in the counter, which is a measure of the input frequency.

Выходы счетчика подключены к разрядным входам преобразователя кодчастота и упразляют его работой. Для запоминания и воспроизведения запомненного сигнала подается управляющий сигнал на шину “память, при этом разрываются цепи сброса двоичного счетчика, а по окончании времени счета блокируются его цепи счета и подается разрешающий потенциал на работу преобразователя код-частота. Импульсы с выхода преобразователя с помощью делителя и фильтра преобразуются в гармонический сигнал с частотой, раем ной запомненной частоте.The outputs of the counter are connected to the discharge inputs of the code-frequency converter and simplify its operation. To memorize and play back the stored signal, a control signal is sent to the “memory” bus, while the binary counter reset circuits are broken, and at the end of the counting time its counting circuits are blocked and the enable potential for the code-frequency converter is supplied. The pulses from the output of the converter with the help of a divider and a filter are converted into a harmonic signal with a frequency equal to the stored frequency.

Современным радиотехничеким средствам часто приходится работать в условиях сложных помех, качество принимаемых радиосигналов при этом неудовлетворительное. Усложнение радиотехнических устройств, повышение мощности передатчиков и чувствительности приемников не всегда дает положительные результаты. Часто приходится вторым входом третьего элемента И, третий вход которого подключен к шине разрешения запоминания, выход третьего элемента И соединен с управляющим входом регистра хранения.Modern radio equipment often has to work in conditions of complex interference, while the quality of the received radio signals is unsatisfactory. The increasing complexity of radio devices, increasing the power of transmitters and the sensitivity of receivers do not always give positive results. Often, the second input of the third element And, the third input of which is connected to the memory enable bus, often has the output of the third element And connected to the control input of the storage register.

На чертеже нальная схема ства.In the drawing, the circuit diagram is.

УстройствоDevice

I формирователь управления, ι элементы И’ 5*7 триггер 9, преобразователь код-частота 11 представлена функциопредлагаемого устройIS сметчик, воспроизповыше20 иметь дело с неустойчивыми, флюктуирующими сигналами, имеющими большой уровень шумов, и искать решения их эффективности приема именно в каналах обработки сигналов.I control shaper, ι elements ’5 * 7 trigger 9, code-frequency converter 11 is a function of the proposed device IS meter, reproducing above 20 to deal with unstable, fluctuating signals having a high noise level, and look for solutions to their reception efficiency precisely in the signal processing channels.

Известное устройство не может обеспечить запоминание частоты неустойчивых флюктуирующих радиосигналов с достаточной точностью. При работе со слабыми неустойчивыми радиосигналами характерно присутствие флюктуационных помех, т.е. возможны случайные существенные уменьшения уровня сигнала или полное кратковременное его замирание. Наличие таких замираний во время счета приводит к неправильной записи числа в а следовательно, к ошибке при ведении сигнала.The known device cannot provide the frequency memorization of unstable fluctuating radio signals with sufficient accuracy. When working with weak unstable radio signals, the presence of fluctuation interference is typical, i.e. Significant significant decrease in signal level or its complete short-term fading are possible. The presence of such fading during the count leads to an incorrect record of the number and, consequently, to an error in the signal management.

Целью изобретения является ние точности устройства.The aim of the invention is the accuracy of the device.

Поставленная цель достигается тем, что в аналоговое запоминающее устройство, содержащее двоичный счетчик, первый вход которого подключен к выходу первого элемента И,второй вход, двоичного счетчика соединен с первым выходом блока управления, первый вход первого элемента И соединен с выходом формирователя импульсов, вход которого является входом устройства, второй вход первого элемента И подключен к второму выходу блока управления, генератор опорных сигналов, выход которого соединен с первым входом преобразователя код-частота, второй вход которого соединен с шиной разрешения запоминания, выход преобразователя код-частота соединен с входом преобразователя код-аналог, выход которого является выходом устройства, второй и третий элементы И, и триггер, введены последовательно включенные детектор и пороговый элемент, и регистр хранения, информационные входы которого соединены с выходами двоичного счетчика, выходы регистра хранения соединены с группой третьих входов преобразователя код-частота, первые входы второго и третьего элементов И подключены к второму выходу бло-50 ка управления, вход детектора соединен с входом формирователя импульсов, выход порогового элемента соединен с вторым входом второго элемента И, выход которого подключен к пе’рвому входу триггера, второй вход триггера соединен с первым выходом блока управления, выход триггера соединен сThis goal is achieved by the fact that in an analog storage device containing a binary counter, the first input of which is connected to the output of the first element And, the second input of the binary counter is connected to the first output of the control unit, the first input of the first element And is connected to the output of the pulse shaper, the input of which is the input of the device, the second input of the first element AND is connected to the second output of the control unit, the reference signal generator, the output of which is connected to the first input of the code-frequency converter, the second input One of which is connected to the memory enable bus, the output of the code-frequency converter is connected to the input of the code-to-analog converter, the output of which is the device output, the second and third AND elements, and the trigger, the detector and threshold element are sequentially connected, and the storage register, information inputs which are connected to the outputs of the binary counter, the outputs of the storage register are connected to a group of third inputs of the code-frequency converter, the first inputs of the second and third elements AND are connected to the second output of the block-50 and the control, the input of the detector is connected to the input of the pulse shaper, the output of the threshold element is connected to the second input of the second element And, the output of which is connected to the first input of the trigger, the second input of the trigger is connected to the first output of the control unit, the output of the trigger is connected to

2S содержит детектор 1 , 2 импульсов, блок 3 пороговой элемент 4, _ 7, двоичный счетчик 8, регистр 10 хранения, , генератор 12 опорных сигналов, преобразователь код-аналог 13 и шения запоминания.2S contains a pulse detector 1, 2, block 3 a threshold element 4, _ 7, a binary counter 8, a storage register 10, a reference signal generator 12, a code-to-analog converter 13, and memory memories.

Устройство работает образом.The device works in a manner.

Входной радиосигнал детектор 1 и одновременно на формирователь 2, где формируется в последовательность импульсов, приведенных к логическим уровням. За калиброванное время счета, на которое блок 3 открывает элемент И 5, импульсы с формирователя 2 заполняют двоичный счетчик 8.The input radio signal is detector 1 and simultaneously to shaper 2, where it is formed into a sequence of pulses reduced to logical levels. For the calibrated counting time, for which block 3 opens the And 5 element, pulses from the former 2 fill the binary counter 8.

шину 14 разрёследующим подается на .где Асч- число импульсов в счетчике; fty - частота радиосигнала·, Т_сч- время счета.the bus 14 is subsequently fed to. where Asch is the number of pulses in the counter; fty is the frequency of the radio signal ·, T _sc is the counting time.

Число, набранное в счетчике 8 за время счета-мера входной частоты радиосигнала, подается на разрядные входы регистра 10. Огибающая радиосигнала с детектора 1 подается на элемент 4. Если уровень радиосигнала достаточен для его дальнейшей обработки, то на выходе элемента 4 низкий уровень напряжения, если мал, то высокий уровень.The number dialed in counter 8 during the counting measure of the input frequency of the radio signal is fed to the bit inputs of register 10. The envelope of the radio signal from detector 1 is supplied to element 4. If the level of the radio signal is sufficient for further processing, then the output of element 4 is low voltage level, if small, then a high level.

По окончании времени счета сигнал с первого выхода блока 3 через элемент И поступает на тактовый вход регистра 10, происходит перезапись числа из двоичного счетчика 8 в регистр 10, затем сигнал с второго выхода блока 3 обнуляет счетчик 8 и происходят снова счет и обновление информации в регистре 10. Если во время счета наблюдается замирание радиосигнала, или он уменьшится настолько, что будет невозможна его ; дальнейшая обработка, то соответственно уменьшение напряжения на выходе детектора 1 вызовет срабатывание элемента 4. Элемент 6 открыт на время счета, так как его первый в^од подключен к второму выходу блока 3, поэтому сигнал с выхода порогового элемента 4 перебросит триггер 9, на втором входе элемента И 7 окажется запрещающий потенциал, т.е. цепь перезаписи в регистр 10 числа из двоичного счетчика 8, в котором оказалось число, не соответствующее правильному значению частоты входного радиосигнала, будет разорвана ив регистре 10 останется число, соответствующее правильному значению частоты радиосигнала, записанное ранее. Сигнал сброса с второго выхода блока 3 помимо обнуления счетчика 8 установит триггер 9 в исходное состояние.At the end of the counting time, the signal from the first output of block 3 passes through the And element to the clock input of register 10, the number is transferred from the binary counter 8 to register 10, then the signal from the second output of block 3 resets the counter 8 and the information is counted and updated in the register again 10. If during the counting the radio signal fades, or it decreases so much that it will be impossible; further processing, respectively, a decrease in the voltage at the output of detector 1 will cause the operation of element 4. Element 6 is open for the time of counting, since its first time is connected to the second output of block 3, so the signal from the output of threshold element 4 will transfer trigger 9, on the second the input of the And 7 element will be the inhibitory potential, i.e. the chain of overwriting into the register 10 the numbers from the binary counter 8, in which there is a number that does not correspond to the correct value of the frequency of the input radio signal, will be broken and in register 10 there will be a number corresponding to the correct value of the frequency of the radio signal recorded earlier. The reset signal from the second output of block 3, in addition to resetting the counter 8, will set trigger 9 to its original state.

Для воспроизведения запомненной частоты на шину 14 устройства подается разрешающий потенциал, при этом закрывается элемент И 7» который блокирует цепь перезаписи информации в регистр 10 и разрешается работа преобразователя 11. Если за все время работы устройства имелся хоть один раз устойчивый радиосигнал, то в регистре 10 окажется число, соответствующее верному значению частоты радиосигнала. Регистр 10 разрядными выходами подключен рядным входам преобразователя частота и тем самым управляет ботойTo reproduce the stored frequency, the resolving potential is applied to the device bus 14, and the And 7 ”element is closed, which blocks the information rewriting circuit to register 10 and the operation of the converter 11 is allowed. If there was a stable radio signal at least once during the entire operation of the device, then in register 10 there will be a number corresponding to the correct value of the frequency of the radio signal. Register 10 bit outputs connected to the row inputs of the frequency converter and thereby controls the bot

888209 6 точность запоминания и воспроизведения частоты неустойчивых флюктуирующих радиосигналов с большим уровнем шумов.888209 6 accuracy of storing and reproducing the frequency of unstable fluctuating radio signals with a high level of noise.

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Claims

The invention relates to an analog technique, in particular to analog storage devices, and can be used for storing and reproducing the frequency of signals in radio devices with frequent information output for subsequent analog processing. A memory device 1 is known, the frequency information of which is represented as a binary number. The closest solution to the technical essence and the achieved result of the invention is an analog storage device 2}, in which, during a calibrated counting time, the pulses generated from the radio signal periodically fill the binary counter and reset the number is a measure of the input frequency. The counter outputs are connected to the bit inputs of the code frequency converter and control its operation. To memorize and reproduce the stored signal, a control signal is fed to the memory bus, thus the binary counter reset circuits are broken, and at the end of the counting time, its counting circuits are blocked and the code-to-frequency potential of the converter is released. The pulses from the output of the converter are converted by a splitter and filter into a harmonic signal at a frequency equal to the memorized frequency. Modern radio-technical means often have to work under conditions of complex interference, the quality of received radio signals is unsatisfactory. The complication of radio devices, increase in transmitter power and receiver sensitivity does not always give positive results. Often, 38 have to deal with unstable, fluctuating signals that have a large noise level, and look for solutions to their reception efficiency in the signal processing channels. The known device cannot ensure the memorization of the frequency of unstable fluctuating radio signals with sufficient accuracy. When working with weak unstable radio signals, the presence of fluctuation disturbances is characteristic, i.e. Significant decrease in the signal level or its full short term freezing are possible. The presence of such fading during counting leads to incorrect recording of the number in the counter and, consequently, to an error when playing the signal. The aim of the invention is to improve the accuracy of the device. The goal is achieved by the fact that in an analog storage device containing a binary counter, the first input of which is connected to the output of the first element I, the second input of the binary counter is connected to the first output of the control unit, the first input of the first element I is connected to the output of the pulse former, whose input is the input of the device, the second input of the first element And is connected to the second output of the control unit, the reference signal generator, the output of which is connected to the first input of the code-frequency converter, the second the input of which is connected to the memory resolution bus, the code-frequency converter output is connected to the code-analog converter input, whose output is the device output, the second and third elements are AND, and the trigger is entered in series with the detector and threshold element, and the storage register, information the inputs of which are connected to the outputs of the binary counter, the outputs of the storage register are connected to the group of third inputs of the code-frequency converter, the first inputs of the second and third elements AND are connected to the second output of the block About the control, the detector input is connected to the pulse driver input, the output of the threshold element is connected to the second input of the second element, whose output is connected to the first trigger input, the second trigger input is connected to the first output of the control unit, the output of the trigger is connected to the second input of the third element And , the third input of which is connected to the memory resolution bus, the output of the third element I is connected to the control input of the storage register. The drawing shows a functional diagram of the device. The device contains detector 1, pulse generator 2, control unit 3, threshold element k, elements I5-7, binary counter 8, trigger 9, storage register 10, code-frequency converter 11, reference signal generator 12, code-analog converter 13 and Bus 14 permits memorization. .: The device works as follows. The input radio signal is fed to detector 1 and simultaneously to shaper 2, where it is formed into a sequence of pulses brought to logical levels. During the calibrated counting time at which block 3 opens element 5, the pulses from shaper 2 fill binary counter 8. where the AHF - number of pulses in the counter} fg) (- frequency of the radio signal; T (c - counting time. The number dialed in counter 8 during the counting time of the input frequency of the radio signal is fed to the bit inputs of the register 10. The bending radio signal from detector 1 is fed to element k If the level of the radio signal is sufficient for further processing, then the output of element 4 is low voltage, if small, then high. At the end of the counting time, the signal from the first output of block 3 through the element I enters the clock input of register 10, overwriting the number from binary counter 8 to register 10, then the signal from the second output of block 3 zeroes counter 8 and the counting and updating of information in register 10 occur again. If during the counting the radio signal is fading or it decreases so much that If it can be further processed, then, accordingly, a decrease in the voltage at the output of the detector 1 will trigger the element, Element 6 is open. for the counting time, since its first is connected to the second output of block 3, therefore the signal from the output of the threshold element k transfers trigger 9 at the second input of element 7 and will have a inhibitory potential, i.e. The rewriting circuit in register 10 of the number from binary counter 8, in which there is a number that does not correspond to the correct value of the frequency of the input radio signal, will be broken and in register 10 there will remain a number corresponding to the correct value of the frequency of the radio signal recorded earlier. The reset signal from the second output of block 3, in addition to zeroing the counter 8, will set trigger 9 to its initial state. To reproduce the memorized frequency, a potential potential is supplied to the device bus 14, and element 7 is closed, which blocks the information rewriting circuit in register 10 and the converter 11 is enabled. If during the entire operation of the device there was a stable radio signal at least once, then in register 10 The number corresponding to the correct frequency of the radio signal will appear. The register 10 with its bit outputs is connected to the bit inputs of the code frequency converter and thereby controls its operation W) (. Gyyy where where is the frequency at the output of the converter 11 i fjj is the frequency of the reference generator, n is the number of bits bodies 11. Using a converter 1 3, the sequence of pulses from the output of converter 11 is converted into a mono signal whose frequency is equal to the memorized frequency of the radio signal .. The proposed memory device allows to significantly improve the efficiency of radio equipment The introduction of the detector, the threshold element and the storage register will continuously monitor the level of the radio signal during the measurement of its frequency and quickly store information in the storage register, and the relative simplicity of the device will significantly improve the accuracy of memory and reproduction of the frequency of unstable fluctuating radio signals from high noise level Formula of the invention Analog storage device containing a binary counter, the first input of which is connected to the output One of the first element And the second input of the binary counter is connected to the first output of the control unit, the first input of the first element And is connected to the output of the pulse shaper, whose input is the device input, the second input of the first element And is connected to the second output of the control unit, the reference signal generator, the output of which is connected to the first input of the code-frequency converter, the second input of which is connected to the memory resolution bus, the output of the code-frequency converter is connected to the input of the code-analog converter, the output which is the output of the device, the second and third elements And and the trigger, characterized in that, in order to improve the accuracy of the device, sequentially connected detector and threshold element are entered into it, and the storage register, the information inputs of which are connected to the outputs of the binary counter, the outputs of the register storage is connected to a group of third inputs of the code-frequency converter, the first inputs of the second and third elements I are connected to the second output of the control unit, the input of the detector is connected to the input of the pulse generator , the output of the threshold element is connected to the second input of the second element I, the output of which is connected to the first input of the trigger, the second input of the trigger is connected to the first output of the control unit, the output of the three | is connected to the second input of the third element I, the third input of which is connected to the resolution bus memory, the output of the third element And is connected to the control input of the storage register. Sources of information taken into account at. Examination 1 USSR Author's Certificate No. 503298, cl. G 11 C 27/00, 197.

2. USSR author's certificate of application no. 2b01568 / 1, l. 6.11 C 27/00, 1978 (prototype).

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