SU888170A1 - Information transmitting and receiving device - Google Patents

Description

one

The invention relates to communication technology and can be used in automation, telemechanics and computer technology, in particular for transferring information between processors and RAM in computing systems.

A device is known for two-way transmission of information 1. Each transceiver node of this device, va, contains a source of information, amplifiers of transmitted and received signals, a complex resistance, a two-wire line. Since there are no parallel-to-serial converters in such a system, the information is transmitted through a parallel code, which requires a considerable amount of cable and is a disadvantage of this system.

It is also known a device for transmitting a signal, 2, which contains a counter of generated pulses, a counter control circuit, communication lines, a register, a counter of received pulses, a control circuit of a received signal. The disadvantage of this device is that after exposure to interference on the communication line, the device’s counters do not provide automatic recoverability and a general reset is required. This leads to the fact that it is not possible to provide a continuous stream of messages. Thus, the field of application of the device is limited to modules, the exchange of information between which can be suspended.

A device for transmitting information, which contains

10 to the transmitting side of the control unit, the outputs of which are connected respectively to the first inputs of the trigger and the element I, the first input of the counter and the first input of the parallel code to serial converter, the output of which is connected to the first communication line, the second input of the trigger is connected to the second communication line, trigger output connected to second input

20 of the And element, the output of which is connected to the third communication lines and the second inputs of the parallel code to serial converter and the counter, the outputs, the converter, respectively, are connected to the third input of the And element and the third input of the converter. On the receiving side, the device contains a serial to parallel converter, the inputs of which are connected to the first and third lines of communication, the output to the first input of the memory unit, a counter whose first input is connected to the third link and the connection is connected to the first the inputs of the switch and the first element AND, the output of which is connected through the first one-shot to the first input of the EL element. OR directly to the trigger input, the output of the trigger is connected to the second input of the OR element, the second input of the first element AND and the second input m of the collider, the first output of which is connected to the third input of the OR element, the second output - through the second one-vibrator to the first input of the second AND element, the second input of which is connected to the output of the OR element, the output is connected to the second communication line

The aim of the invention is to increase the information content and speed of the device.

The goal is achieved by the fact that in a device for transmitting and receiving information, containing on the transmitting side a control unit, the first output of which is connected to the first trigger input, the output of the trigger is connected to the first input of the first element I, the output of which is connected to the first communication line, the second output of the control unit through the parallel code to serial converter is connected to the second communication line, on the receiving side there is a counter, the input of which is connected to the first communication line, a trigger whose output is connected to the first The input of the OR element connected to the third communication line and the first UJiOK are entered into the fourth communication line, on the transmitting side - the pulse shaper, the second and third elements AND, the input of the pulse shaper is connected to the first output of the control unit, the first output is the second the input of the first element is And, the second output is with the first input of the second element And, the output of which is connected to the fourth communication line, the second input of the second element And is combined with the Bypass of the control unit and connected to the output of the trigger, the third output of the control unit is connected the first input of the third element is And, the second input of which is connected to the third communication line, the output is connected to the second input of the first device, at the receiving side the address registers are entered, the second memory block and the modulo two, the output of which is connected to the second input of the element OR , the first input of the modulo two is combined with the first inputs of the first and second memory blocks, the second inputs of which are combined and connected to the second communication line, the third input of the second memory block is combined with the first input of the first address register and the input m trigger and is connected to the fourth link, the third input of the first block

the memory is combined with the first input of the second address register and connected to the first communication line, the output of the counter is connected to the combined second inputs of the first address register and the modulo two, the output of the first address register is connected to the fourth input of the first memory block and the second input of the second register an address whose output is connected to the fourth input of the second memory block.

A block diagram of an apparatus for transmitting and receiving information is shown in FIG. one; in fig. 2 - timing charts of the device. The transmitting and receiving sides of the device are conventionally highlighted by a dashed line (Fig.

On the transmitting side, the device contains a control unit 1, a pulse shaper 2, a trigger 3, And 4, 5, b elements, a parallel-to-serial code converter 7. The transmitting and receiving sides are connected by communication lines 8, 9, 10, 11. The receiving side contains the element OR 12, the trigger 13, the counter 14, the first 15 and the second 16 address registers, the adder 17 modulo two, the first 18 and the second 19 blocks memory

To explain the mechanism for transmitting and receiving information, we will make the following explanations.

Block 1, using the master GA of the computing system (not shown in FIG.), Forms a sequence at its first output (a series of rectangular pulses G1 1 г 2). The shaper 2, using it, forms at its outputs two series of impulses (two phases) Г2, ГЗ, operating in time synchronously with the pulses P. In the first 15 and second 16 registers of addresses the addresses of the cells of blocks 18, 19 are stored. recording information. The address of the cell in which information is recorded from the outputs of registers 15, 16 is fed to the corresponding inputs of blocks 18/19. The address of the memory block cells, which is used to read information from these blocks, is generated at the other inputs of the memory blocks. A modulo 17 modulator 17 forms at its output a signal identified with the presence of information (suppose logical 1) if the logic signals at its inputs differ. Transducer 7 converts a parallel code into a serial one. The transmitted information word is divided: by converter 7 into two halves. Initially, at the output of converter 7, the first half of the transmitted word is set, and then the second. The first half of the transmitted information word is always recorded in block 18, and the second half is recorded in block 19;

A device for transmitting and receiving information operates as follows.

Unit 1 generates an information word to be transmitted at the second output, which is fed to the input of converter 7. At the same time, at the third output, unit 1 generates a signal that indicates that the information word is prepared for transfer. This SGS arrives at the first input of the AND element 6, to the second input of which from the communication line 10 enters a signal permitting the transmission of a serial code. The signal permitting the transmission of the serial code enters the line 10 in the event that in blocks 18, 19 there are free cells for recording information. The fact of the presence on the transmitting side of an information word ready for transmission and the presence of a signal permitting the transmission of a sequential code on line 11 sets the element 6, which in this case also forms logical output 1. Logical 1 is fed to the second input of trigger 3. Trigger 3 located before that, in logical O on the leading edge of the pulse G1, it switches to logical 1. Logical 1 from the output of trigger 3 indicates to block 1 that during the cycle G1 the information word set on the second output of block 1 will be transmitted but. According to this logical 1, block 1, at the moment of the action of the falling edge of the pulse G1 for the converter 7, generates a signal according to which it establishes: at its output, the second half of the transmitted information word. Thus, at the time of the action of the pulse G1, the first half of the information word is transmitted along line 11, and during the pause of the pulses of the series G1 of the second.

The trigger 3 is in a state of logical 1 for at least the duration of a cycle of a series of pulses G1. During this time, the G2 impulse arrives in line 8, and the GZ impulse in line 9. The impulse G2 of line 8 accompanies the first half of the information word transmitted along line 11, and the impulse GZ on line 9 is the second. The impulse G2 from line 8 enters block 18 and writes the first half of the information word there, the impulse GZ from line 9 enters block 19 and writes the second half of the information word there.

The cell address by which the information word is recorded in blocks 18, 19 is generated by counter 14 and stored during the recording time of information in registers 15, 16. Suppose that in the initial state the contents of counter 14 and registers 15, 16 are zero. When transmitting the first half of the word in line 8, the act of the impulse G2, WHICH increases the content of the counter 14 by one. The same impulse writes the first half of the information word to block 18 in the cell number O, since the contents of register 15 are equal to zero during writing and overwrites the zero from register 15 to register 16. When transmitting the second half of the word, line 8 acts on the impulse GZ which is written in. Register 15, the contents of counter 14 (in this example, a unit is recorded in register 15) and writes to block 19 in the cell number O the second half of the information word. Thus, the information word will be written in whose. .ki with number O. When recording the next information word, the cell number 1 will be taken, then

0 number 2, etc. The maximum counter reading 14 is equal to the maximum number of memory cells in the block.

18 (19).

Block address 18, 19

5 to which information is read, the format of the NSHpyeTCH on the first inputs of blocks 18, 19. The reading of information from blocks 18, 19 occurs in the same order as the recording, i.e. the contents of the cells with the number O are initially read, then with the number 1, etc., if only the information has been previously written in them. When using the device, the following situations are possible. Current read address

5 times different from the address of the entry. This suggests that in blocks 18,

19 there are free cells where new information can be written to. At the output of the adder -17 is formed

0 logical 1, which through the element OR 12 enters the line 10 and allows the transmission of the next information word. In another situation, the write address and read address are the same. This happens when blocks 18, 19

5 are completely free (the number of recorded information words is equal to the number of read words), or when blocks 18, 19 are fully occupied (the number of read words was insufficient and all cells of blocks 18, 19 were filled with information). If, at the same write and read addresses, the blocks 18, 19 are free, this means that the reading of information in time occurred later than the write. Conversely, if the recording was made later than reading, then blocks 18,

19 will be completely occupied by you. Trigger 13 remembers what was the last

0 write or read. If the last one was a read, then the trigger 13 is set to the state of logical 1, this logical 1 goes through the OR element 12 to the line 10 to allow the transfer of information. Ko05

Yes, trigger 13 is in the state of logical O with the same write and read addresses, blocks 18, 19 are fully occupied, at the inputs of the element OR 12 are logical O, and in line 10 a signal is generated prohibiting the transmission of information.

When a prohibitive information transmission signal is output in line 10 at the output of element Ib logical o, trigger 3 remains in the state logical o and prohibits the transmission of lines 8, 9 of the signals corresponding to the phases G2 and GZ, respectively, and also indicates to the block-1 that the prepared An information word has not yet been transmitted for transmission. Block 1 continues to hold the information word at its second output, and logical one at the third output, until transmission permission signal has arrived from line 10 and trigger 3 switches to logical 1).

In comparison with the known device, the information content of this device is increased. In the known device, one machine clock is used to record information represented by a parallel code into a parallel code converter, a serial signal is generated in the second clock, which follows the first half of the information word on the communication lines, and the second clock signal is generated in the third clock, which accompanies the communication line is the second half of the information word. Thus, the transfer of one information word spends three machine cycles. In the proposed device, two clock cycles are spent on transmitting one information word, information is recorded in converter 7 in the first cycle and the first gate signal is formed in line 8, the second gate signal is output in line 8 and the second output of block 1 in the second cycle Prepared for transmission to the next information word. Since a smaller number of machine cycles is spent to transmit the information word on the transmitting side, the information content of the proposed device will be higher, i.e. In the same time interval, more information words will be transmitted.

In the proposed device in comparison with the known reduced delay in the transmission of information. In the known device, the transmission delay is longer, since the moment of recording the information in the parallel-to-serial converter until the formation of the first gating pulse in the communication line goes through the machine time j. In the proposed device, this delay is eliminated. In the famous

The device information word is delayed from the receiving side by one clock cycle, which is spent on overwriting information from. serial-parallel converter to memory block. In the proposed device, this rewriting procedure is absent, and the formation of a parallel code to be further processed takes place directly in the memory blocks, i.e. increases the speed of the device.

Claims (3)

Invention Formula A device for transmitting and receiving information, containing on the transmitting side a control unit, the first output of which is connected to the first trigger input, the trigger output is connected to the first input of the first element I, the output of which is connected to the first communication line, the second output of the control unit through a converter parallel code in serial is connected to the second communication line, on the receiving side - a counter, the input of which is connected to the first communication line, trigger, the output of which is connected to the first input of the OR element connected to t The second line of the communication line, and the first block of memory, which is connected with the fact that, in order to increase the information content and speed of the device, a fourth line of communication is entered into It, on the transmitting cfopOHe pulse shaper, the second and third elements And, the input pulse generator connected to the first output of the control unit, the first output to the second input of the first element And the second output to the first input of the second element And the output of which is connected to the fourth communication line, the second input of the second element And combined with the input of the control unit and The third output of the control unit is connected to the first input of the third element I, the second input of which is connected to the third communication line, the output is connected to the second input of the first trigger, the address registers, the second memory block and the modulator are entered at the receiving side. two, the output of which is connected to the second input of the OR element, the first input of the modulo two adder is combined with the first inputs of the first and second memory blocks, the second inputs of which are combined and connected to the second communication line, the third input of the second memory block bedinen to a first input of the first address register and the input of the flip-flop and is connected to a fourth line connection, the third input of the first memory block is combined with the first input of the second address register and connected to the first communication line, the output of the counter connected to the combined second passages of the second register of the address and modulo two adder, the output of the first register of the address is connected to the fourth input of the first memory stick and the second input of the second address register, the output of which is connected to the fourth input of the second memory block. Sources of information taken into account in the examination . USSR author's certificate 499677,. cl. H 04 B C / 5O, 1973. 2. Accepted for Japan  50-24565, class From 06 F 11/00, published 1975. 3. USSR author's certificate for application 2883078 / 18-24, cl. G 08 C 19/28, 1978 (prototype). n i t m: g H; I g . e l one / Y / x / L . .Ltl-j IG