SU883930A1 - Analogue-digital multiplying device - Google Patents

Description

The invention relates to the field of computing and can be used for precision multiplication of analog signals. Devices for intermixing analog signals are known, comprising a following ADC consisting of an array of resistors, a comparator, keys, a reversible counter, a clock generator, and a multiplier; TAPA til However, a mechanical increase in the number of races; The closest in technical essence to the proposed object is an analog-digital multiplying device containing the sources of the first factor, the second multiplier and the reference signal, two digital-adjustable resistors, an operational amplifier and a digital information selection circuit 2. The disadvantage of this device there is insufficient accuracy of the multiplication operation, and improving the accuracy of the multiplying device by increasing the number of bits is not promising, since it reduces the speed CTBA doubled for each additional bit of the object of the invention -. ochnosti multiplier Apparatus increase without performance improvement. The goal is achieved in that an analog-digital multiplying device containing the source of the first factor, the source of the second factor, the source of the reference signal, a reversible binary counter, serially connected first digital-controlled resistor, operational amplifier and the first low-pass filter, the output of which is the output devices, the second digitally controlled resistor, comparator and clock generator. pulses, the output of which is connected to the counting input of the reversible binary counter, the control input of which is connected to the output of the comparator, and the discharge outputs of the reverse binary counter are connected to the control inputs of the first and second digital-controlled resistors, the information inputs of which are connected to. Responsible to the OUT1M source of the first

the multiplier and reference source, the output of the second digital-controlled resistor is connected to the first comparator input, a second low-pass filter, a differential amplifier, an adder and a triangle pulse generator are input, the second low-pass filter input is connected to the output of the second digital-controlled resistor, the output of the second low-pass filter is connected to the inverting input of the differential amplifier, the non-inverting input of which is connected to the source output of the second factor and the output to the first input of the adder, the second input of which is connected to the output source of the second factor, the third input to output the triangle wave generator, and an output - to a second input of the comparator.

FIG. 1 shows a block diagram of an analog-digital multiplying device; in fig. 2 a, b, c are diagrams explaining the operation of the device.

The analog-digital multiplying device contains a comparator 1, digital-controlled resistors (LRCs 2 and 3), a reversible binary counter 4, a clock generator 5, low-pass filters b and 7, an adder 8 differential amplifier 9, a triangular pulse generator 10.

The operational amplifier 11, the output of the digital-controlled resistor 2 is connected to the input of the low-pass filter 7 and the first input of the comparator 1. The device also contains the sources of the first factor 12, the second factor 13 and the reference signal 14.

The information input of the digital-controlled resistor 2 is connected to the source of the reference signal VR, and the control inputs are connected to the output of the reversible binary counter 4. The output of the low-pass filter 7 is connected to the inverting input of the differential amplifier 9, the non-inverting input of which is connected to the source of 1 f and the second input of the adder B ... The output of the differential amplifier 9 is connected to the first input of the adder 8, the third input of which is connected to the output of the triangular voltage generator 10. the output of the adder 8 soednen the second input of the comparator 1 whose output is connected to the control input of the reversing-COUNT ika 4, the counting input of which is connected to the output of clock pulse generator

5. The output of the digital-controlled resistor is connected to the input of the operational amplifier 11, the output of which is connected to the input of the low-pass filter

6. The information input of the digital-controlled resistor 3 is connected to the source of the second of the multiplied voltages 1, and the control inputs to the output of the binary reversing counter 4.

The device works as follows.

When an analog voltage V is applied to the input of comparator 1, this voltage is compared with the voltage Vg formed at the output of the digital-controlled resistor 2 when summing up the binary-weighted currents from the source of the reference voltage Vg. The magnitude of the voltage Vo is in one-to-one correspondence with the position of the analog switches of the digital-controlled resistor 2, and these, in turn, are controlled by the binary code from the output of the reversible counter 4, say, the difference IV-, 1. - WoJ O, while at the output of the comparator 1 is low potential, the reversible counter 4 operates in the subtraction mode, the voltage decreases in jumps equal to the weight of the least significant bit. When changing the sign of the difference, i.e. at V-,) - | Vot о, the comparator 1 switches to the high potential position and the counter switches to tracking mode and remains in this position until - VQ again changes sign.,. Thus, the next ADC (formed by blocks 1, 2, 4, and 5) of the ADC operates in the yoke mode near the Vo tuning point (Fig. 2a) with the frequency fy / i, where fr is the frequency of the clock pulses. In this case, the voltage plots at the output of LRC 2 will look like that shown in FIG. 2a When the input voltage V varies within the deadband uVo, i.e. when lV., t-IVol uVj, the nature of the work does not change, therefore Vg does not change, which determines the methodological error of the transformation. As soon as IVol Vo, the next ADC (blocks 1, 2, 4 and 5) begins to process downward | V-il - IVsl until - WQ becomes uVg and the yaw is resumed in a new equilibrium point V (FIG. 2a). To reduce the dead zone in the proposed device, the input signal V is summed in the adder 8 with a triangular voltage from the output of the generator 10, the full swing of this voltage is equal to the insensitive zone AVo. The frequency of the triangular voltage is an order of magnitude less than the frequency of the yaw, i.e. equal to f t / io. Suppose V ,, is in the middle of the dead band of AV5, while the triangular voltage does not leave the zone (Fig. 26), the operation of the ADC in this case is similar to the work of the known one. When increasing, for example, the voltage V by the value of iV, the output voltage of the adder 8 will increase by l triangle voltage

rises (fig. 26) and crosses the border of the dead zone, the comparator 1 at the first moment is set to a state with logical 1 at the output, the reversible counter 4 goes into the adding mode and changes its state to the low-order unit, this digital word will switch the keys the digital-controlled resistor 2 so that the output voltage jumps to i. This voltage will switch comparator 1 to a position with a logical output O, counter 4 will work on subtraction per unit of the least significant bit and, thus, this part of the period of the triangular ADC voltage will scour in the higher zone vjj, and the rest of the period - lower zone Ud.Napr-. The input voltage of the digital-controlled resistor 2 is supplied to the low-pass filter 7 and the constant component Uf is extracted. This constant composition is compared in the differential amplifier 9 with the input voltage V, and the difference is fed to the input of the adder 8. Moreover, the sign of this difference is chosen so that the displacement of the triangular voltage occurs in the direction of decreasing this difference. The low pass filter 7, the differential amplifier and the adder 8 form an additional tracking loop, reducing the error due to instability — the elements used and spurious output voltage spikes.

FIG. 2 shows that a smooth change in the input voltage leads to the appearance of yaw impulses in one insensitive zone and to their disappearance in another, which, in turn, leads to a change in voltage at the output of the low-pass filter by the value -, (because -.- restig YQ) per pulse, therefore, the resolution of the conversion is increased by 10 times f compared to the known, and with it the tracking accuracy for the input signal. Since the control inputs of the keys of the digital-controlled resistors 2 and 3 are connected to the same digital output of the reversing counter 4, then at the output of the digital-controlled resistor 3, the nature of the voltage change will be the same as at the output of the digital-controlled resistor 2 However, since the second of the multiplied voltages V is used as the reference voltage of the digital-controlled resistor 3, the output voltage at the output of the lower filter 11 will also be proportional to the value. Thus, the control inputs of the digital-controlled resistor 3 are supplied with a digital word from the output of the reversible binary counter, and

The second of the multiplied voltages M is fed to the information input. This digital word is converted to an analog signal Vg, at the output of operational amplifier 11, this output voltage can be represented as vice.

4 ", (a, .l-4 ... anO, where a-a„ - the coefficients are equal to zero, if the output binary word in

o this bit is zero and one if the input binary word in the given bit is one. The value, in parentheses, is directly proportional to the second factor V, up to

5 least significant bit, since the digital word expressed by the coefficients a, al .... a is obtained as a result of voltage conversion to binary code, therefore

0 (, iu-2 + ... c (na) i; Vi,

then Ugb, v.

Thus, it can be concluded that the summation of the input voltage with a triangular one leads to a 5 decrease in the discretization step of the ADC, and consequently, to an increase in the accuracy (multiplication of analog voltages).

Claims (2)

1. Design and use of operational amplifiers. Ed. J. Graham et al. M., Mir, 1974, p. 364-370. 2. Smolov V.B. et al. Continuous computing machines. M., Higher School, 1964, p. 358361, Fig. VI-23 (prototype).