SU881871A1 - Analogue storage device - Google Patents

Description

I

The invention relates to computational and instrumentation technology and is intended for well-known digital converters, acquisition and transmission systems, data, and analog signal processing devices.

Known analog storage devices built on two capacitors and three amplifiers 1, as well as built on two capacitors and two amplifiers 2.

A disadvantage of the known devices is the low accuracy, the lack of compensation for such additive components of error, as voltages. the bias of the included amplifiers. The low accuracy and poor stability of the device parameters are caused by the absence of a stabilizing negative feedback loop in the storage mode.

The closest to the proposed technical entity is an analog storage device containing an amplifier, the first input of which is connected to the device input and common through the first and second keys

the bus, the second input of the amplifier is connected to its output and one lining of the first capacitor, the second lining of which is connected to the output of the device and through a third key to the common bus, as well as the second capacitor, one lining of which is connected to

10 by a common bus, and the other through the fourth and fifth keys are connected to the first amplifier input and device output. In the storage mode, the output voltage Ugbix of the known device is a function of the input voltage Ug, at the time of transition from the recording mode to the storage mode, and also depends on the parameters of the gain amplifier A and the voltage

20 her displacement

UBXO (1 -} g) -B- (y) (1)

and

8S

hence the device’s errors are

Liv, x UBXO-; (2)

Afc PO- .. (3) Thus, the device is compensated for the bias voltage, which is a positive feature 3.

A disadvantage of the known device is the need for a three-stroke operation mode: the storage mode on the first driver of the bias voltage of the amplifier (only the second and third keys are closed); recording mode (only the first and fifth keys are closed); storage mode (only the fourth key is closed).

Three-stroke operation mode requires a complicated key management device circuit. The storage time of the bias voltage of the amplifier is the dead time of the device, due to which it is necessary to reduce either the recording time of the device or the storage time or increase the total time of one full three-cycle operation cycle of the device. In the first two cases, the underdischarge error of the second capacitor increases or, after analog storage, it is necessary to switch on circuits that have time to process the stored signal in a shorter period of time. In the third case, the spectrum of input signals that can be reduced (Processing by the storage device, which causes reduce the speed of the device.

The purpose of the invention is to improve the accuracy and speed of the device.

The goal is achieved by the fact that in an analog storage device containing storage elements, such as capacitors, an amplifier whose output is connected to the output of the device, keys and a zero potential bus, one of the plates of the first capacitor is connected to the outputs of the first and second keys and to the input of the third key, the output is connected to the first input of the amplifier and to one of the plates of the second capacitor; the other, the cover of the second capacitor is connected to the zero potential bus, the input of the first switch is connected to the input of the device, the input key is connected to the output of the amplifier and to the input of the fourth key, the output of which is connected to another plate

the first capacitor and the second input of the amplifier.

The drawing shows a functional diagram of the proposed device.

The device contains storage elements, for example capacitors, 1 and 2, amplifier 3, switches 4-7 and bus 8 of zero potential.

The device works as follows.

With closed keys 4, 6 and 7 and open key .5, the device operates in the recording mode. The second capacitor 2 is charged by the input voltage UBX at the input. devices

Uc2 wiv7. (4)

The voltage Ugbu at the output of the device is slightly different from the input and is

ebix-j Ceo + UaO, (5) where A, fo is the gain and the bias voltage of the amplifier, AS 1.

The first capacitor 1 is charged BEFORE voltage close to about

Uc, ivh-ib, x ivl-t A-oA. (6)

Open key 5 is under DC voltage, close to zero, which is beneficial for its operation. With the closed key 5 and the open keys 4, 6 and 7, the device switches to the storage mode. In this case, the capacitors 1 and 2 are fixed voltage, corresponding to

Ucio-Jexo TTA ° TGA Ucio Uexo,. (8) where Uex is the voltage at the input of the device at the moment of transition from recording to storage mode.

 -, i The voltage at the output of the device in the storage mode is changed to the value

OUT, A (, O + Uc2o). (9) Taking into account the values of Uc, o and from 5 expressions (7) and (8), the output voltage of the device is

and ... and., .... (10)

OR1L OLY f h)

From expression (10), it is possible to find the error components of the analog

0 storage device: D Ugbw the error due to the limb gain of the amplifier 3 and the error caused by the presence of the bias voltage of the amplifier 3

55 D Uex, JT - / 11)

Aes e. (“2)

Claims (3)

Thus, the proposed device is 2A times more accurate than the known one. This eliminates the dead mode of the circuit, reducing the speed of the storage device. In addition, in storage mode, key 6 operates with minimal voltage drops, since it is connected between the second capacitor 2 and through the second key 5 is connected to the output of the device. The voltages at the input and output of the third key 6 are different from the input memorized voltage by the value of DWi which is very close to zero. Due to the large gain factor A 1 amplifier 3, the voltage of its inputs is very close, so the minimum voltage difference is close to zero applied to the fourth key 7, included between the output of the device and the second input of the amplifier 3. The operation mode of keys 5–7 with minimal voltage drops contributes to the increase in the device performance due to the small charge times of parasitic key capacitors by small voltage drops. Analog memory device containing storage cells, for example capacitors, an amplifier whose output is connected to the output of the device, keys and a zero potential bus, characterized in that, in order to improve the accuracy and speed of the device, one of the plates of the first capacitor is connected in it with the outputs of the first and second keys and the input of the third key, the output of which is connected to the first input of the amplifier and one of the plates of the second capacitor, the other plate of the second capacitor. connected to the zero potential potential, the input of the first switch is connected to the input of the device, the input of the second switch is connected to the output of the amplifier and to the input of the fourth switch, the output of which is connected to another plate of the first capacitor and to the second input of the amplifier. Sources of information taken into account in the examination 1.Patent of France I 2379879, ATP 27/02, published. 1977. 2. US patent number 3851260, CL. 328-151, published. 1974. 3. US patent number 3716800, CL. 328-151, published. 1973 (prototype).