SU879489A1 - Device for measuring electric power factor - Google Patents

Description

I

This invention relates to instrumentation. technology and is intended for use in measurements of the coefficient of electrical power in electrical networks.

A device for measuring the power factor is known, comprising a phase shifter, controllable dividers, an adder, a comparison circuit, integrators, and a readout device D3.

A disadvantage of the known device is the limited range for measuring the electrical power factor.

It is also known a device for measuring the electric power ratio, comprising a thyristor switch, the control electrode of which is connected to a pulse shaper, and a cathode to a load resistor, a voltage stabilizer, the output of which through a filter and amplifier

connected to the thyristor anode, amplitude detector, whose input is connected to the load resistor, and the output to the registration unit 2 /.

The disadvantage of this device is that the electric power factor is measured only for angles ranging from 0 to.

The aim of the invention is to expand the measuring range.

This goal is achieved by introducing a thyristor switch, averaging and normalizing devices, an adder, a zero-organ and a voltage polarity switch, in the device for measuring the electrical power factor, which contains a voltage regulator, a pulse shaper and a load resistor. moreover, the output of the voltage regulator is connected to the input of a symmetric thyristor switch, the control input of which is connected to the output of the pulse former and to the control input of the averaging device input coupled to the output load resistor and thyristor switch, and an output of the zero-organ and switch the polarity of the reference voltage - the first input of the adder, Auto swarm input coupled to an output of the normalizing apparatus. Fig. 1 shows the functional diagram of the device for measuring the electrical power factor; Figs. 2, 3 are timing diagrams explaining the operation of the device. The device contains a voltage regulator, a pulse driver 2, a symmetric thyristor switch 3, a load resistor 4, a serial device 5 connected in series, a normalizing device 6, an adder 7 connected in series to a zero-voltage device 8, at. than the output of stabilizer 1 is connected to the input of a symmetric thyristor switch 3, the control input of which is connected to the output of the driver 21i and to the control input of the device 5, the input of the device 5 is connected to the output of the switch 3, which is connected to the resistor 4 It is connected to the input of the null organ 8, and the output of the switch 9 is connected to the second input of the adder 7,. The network voltage is applied to the stub. LIZATOR 1, which maintains it at a given level. The amplitude-stabilized voltage is applied through the switch 3 to the load resistor 4. At 1. The control input of the symmetric tris switch 3 receives pulses that are produced by the driver 2, the input of which is connected to the controlled current circuit i. The shaper 2 produces pulses only at the zero-crossing times of the increasing controlled current curve with a period equal to the controlled current period, the pulses arrive at the start of key 3 and to the control input of the device 5. If the controlled current lags behind the controlled voltage by an angle (see, Fig. 2), the control pulse arrives with a delay of an angle H with respect to the zero crossing time of the ascending curve of the sinusoidal voltage, and the key 3 is opened with the arrival of po9. 4 positive half-waves of sinusoidal voltage, with a delay relative to its beginning by an angle f. At the same time, on the resistor 4, a part of the positive half-wave of the sinusoidal voltage is located, which is enclosed between angles-H and JT (see Fig. 2d). If the monitored current is ahead of the monitored voltage by the angle M, (see FIG, W), then the control pulse arrives at key 3 ahead of angle угол with respect to the moment of zero crossing of the sinusoidal voltage curve, and the key 3 opens with the arrival negative half-wave of sinusoidal voltage, with behind, g holding relative to its beginning on angle JT - H At the same time on the resistor 4 a part of the negative half-wave of sinusoidal voltage enclosed between the angles X - H and OT is separated (see, Fig, 3 d) , Impulses coming from the exit The clock 2 and the next with a repetition period equal to the period of the monitored voltage are controlled by the device 5, which can be built on the basis of the integrator with the memory feedback. At the output of the device 5, a constant voltage equal to the average value of the half-period portion of the sinusoidal voltage allocated to the resistor 4 forms. Moreover, if the controlled current lags behind the controlled voltage, the polarity of the output voltage of the device 5 is positive ( cm, fig, 2, d), and if the current is ahead of the monitored voltage, then it is negative (see fig, 3, d). From the output of the device 5, the average value of the half-period of the sinusoidal voltage goes to the device 6, which is rationing cases Tel voltage from the output device 6 normalizing the mean value of the sinusoidal half-cycle portion voltage is supplied to the adder 7 pervly input, a second input of which the output from the switch 9 is supplied reference voltage. The magnitude of the reference voltage is 1 V, and its polarity is set by the switch 9, depending on the polarity of the average value of the voltage at the output of the device 5. The switch 9 is controlled by the zero-organ 8, which, for positive polarity, the output of device 5 produces a voltage sufficient to switch 9 to a second input of the adder 7 a negative polarity reference voltage (see Fig. 2, e) and, conversely, with a negative polarity of the output voltage devices 5 - the positive voltage of the positive polarity (see Fig. 3, e). At the output of the adder 7, we obtain a voltage corresponding to the electric power factor normalized in units of voltage, the value of which when the phase angle f changes in the range from O to JT and from O to - JT can take values from +1 V to -1 V (see Fig. 2, g and 3, g),.

Claims (2)

1. The author's certificate of the USSR 708250, cl. G O R 21/06, G 01 R 25/02, 03.10.77. 2. Authors certificate of the USSR 646265, cl. G 01 R 21/00, 09.11.77 (prototype). a, uft uft in 6 If about -g C -6 d i-LnSlftftat in-exercise INP Z, g ABOUT ,; i WITH t. Co3f f O Fi.g