SU869024A1 - Device for determining analogue-digital conversion error - Google Patents

Description

one

The invention relates to computing and measurement technology and is intended for use in automated information processing systems.

A device is known that contains an analogue 6-zi 1 level 21 converter, a control and synchronization unit, an adder, a unit for calculating statistical characteristics, an indicator, a switch, a test analog signal generator, and a test 11 oscillator 1.

The disadvantages of this device are the impossibility of continuously monitoring conversion errors and low reliability of operation.

The purpose of the invention is to provide continuous monitoring of errors in the Conversion Process of an arbitrary input analog signal and to demonstrate the reliability of the conversion.

This goal is achieved by the fact that the device for determining the errors of the analog-to-digital conversion, containing the analog-to-digital converter, the input of which is connected to the input bus and the output to the first output bus, is an adder.

the statistical characteristics calculation unit, the input of which is connected to the output of the vessel, the indicator, the input of which is connected to the output of the statistical characteristics calculation unit, and the output to the second output bus, the control and synchronization unit, the first output of which is connected to the synchronization inputs of the analog-to-digital converter, a block for calculating statistical characteristics and an indicator; a digital filter, a digital locking block and a valve, the first input of which is connected to the output of the analog digital the converter, the second input - with the second control and synchronization output, and the output - with the digital filter input, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the digital delay unit, the input of which is connected to the output of the analog-digital converter, and the inputs synchronization of the digital filter and the digital delay unit are connected to the first output of the control and synchronization unit.

The drawing shows a block diagram of the device.

The device contains an analog-to-digital converter (ADC) 1, a control and synchronization unit 2 (BEAD), an adder 3, a unit 4 for calculating statistical characteristics (BVSH), an indicator 5, a valve b, a digital filter (DF) 7 and a block 8 for digital delay ( CH

The device works as follows.

When the input signal arrives, the ADC 1 samples the input analog signal at the moment of arrival of the pulse from the first output of the BEAD 2 and converts this analog sample to a digital code. A digital sampling code is provided at the operating output of the device. In this case, the WCD 2 has two outputs, through which synchronized clock pulse sequences are synchronized. The clock pulses of both sequences follow with constant periods. The first sequence of clock pulses (the sequence from the first output) synchronizes the operation of the ADC 1. The period of the pulses of the second sequence (the sequence from the second stage) follows an integer number of times more than the period of the pulses of the first sequence, and the moments

the occurrence of pulses of the second sequence coincides with the moments of the corresponding pulses of the first sequence.

. The operation of the valve 6 is controlled by a second sequence of clock pulses (a sequence from the second output of the WCD 2) so that the valve output is given a digital code present at its input only at the moments of the occurrence of the clock pulse. Otherwise, there is zero at the valve outlet. These codes are fed to the input of the DF 7, the output of which is given a sequence η; frc codes with a follow-up period coinciding with the output period of the ADC 1 digital samples, but with this, not all digital sample codes from the ADC 1 , ac pass. Instead of missing samples of the ZF 7, they come well; In addition, the samples from the ADC 1 are fed to the input of the block 8 CH.

Block 8 of the device CZ is set to a delay time parameter equal to the delay time of the ZF 7. Therefore, the digital bur (sequences received for two inputs of adder 3 are equal and opposite in sign only if there is no conversion error, and then the output of adder 3 is output zeros. If the sum of the pair of samples is not equal to zero, then this indicates the presence of a conversion error that equals the value of the sum obtained at the output of the adder 3. The values of the errors from the output of the adder 3 are received at BVSH 4. i At the output of BVSH 4, the corresponding statistical characteristics of the input sequence are output in digital form. Indicator 5 converts the input digital characteristics into a visual image that is easy for the operator to perceive. The visual information of indicator 5 serves as a control output signal of the device, i.e. continuous conversion control resulting in improved signal processing results

Claims (1)

1. Collection of the II Regional Workshop Hardware control of analog-digital and digital-analog converters. Gorky, GUI them. f.h. Zhdanova, 1978, p. 15-20 (prototype).