SU868765A1 - Information processing device - Google Patents

Description

(54) DEVICE. FOR PROCESSING INFORMATION

I

The invention relates to a computing tech- nics and can be used in digital computing systems oriented to the processing of vectors (arrays of operands).

Information processing devices are known that contain adders, counters, registers, switches, memory blocks, command and address generation nodes 1.

The disadvantage of these devices is limited functionality due to the need to perform complex and lengthy procedures for transferring control on the results of processing operands, the length of which differs from some predetermined fixed value.

Computer systems are also known in which the control transfer condition is generated from the processing results of the variable-length operands. The length of the operands is specified in a certain range with a certain discrete: one bit 2, one byte 3.

The disadvantage of such systems is that the operands in them are treated as scalar values. Thus, for example, when performing a comparison operation in the IBM / 370 system, two fields up to 2 bits in length are considered as two numbers and one of the three signs is formed — more, equal, less.

At the same time, quite often such a long operand is not a scalar value, i.e. one number, and is a vector, i.e. array of values When analyzing such an array, it is convenient to use signs summarized over the entire array: whether there are at least one among the values that satisfy the condition to be checked, for example, whether there is at least one defective or non-defective product in the batch (hereinafter one unit); whether all values satisfy the condition being checked, for example, whether all the products in the batch are qualitatively or poorly fulfilled (hereinafter, the condition is all ones).

20

Collected signs allow in certain cases to significantly speed up the decision due to the J of the number of conditional check operations. It is also useful to be able to ignore the results of processing individual elements of the array, for example, the failure of measuring devices when processing an array of measurement results, when generating generalized signs. Closest to the proposed device is a computer system containing arithmetic logic unit, several devices for generating signs of the results of arithmetic logic operations, a register of the length of the field being processed and a register of control transfer conditions, with the outputs of the arithmetic logic device connected to the inputs of devices for shaping Signs The disadvantages of the known device are the limited performance of the system due to the lack of the possibility of forming a generalized prize. results of operations, if the field being processed is an array of values, as well as the impossibility of prohibiting the use of processing characteristics of individual groups of bits (i.e., signs of some operation results) when generalizing characteristics of the field being processed are used. The purpose of the invention is to increase the performance of the computing system by extending its functionality, which allows reducing the number of operations to analyze the processed field, considered as an array of operands. The suppressed goal is achieved by the fact that in the device containing the arithmetic logic unit, the output of which is connected to the first input of the block comparing the results of arithmetic and logical operations, the length register is processed. Bended field and M registers of control conditions, entered the register of the length of the operands, M blocks for the formation of generalized signs of arithmetical-logical operations and a phrase, with the first input of the i-ro block for forming generalized signs of arithmetic-logical operations (i 1, M) connected to i- the second input of the block comparing the results of arithmetic logic operations, the second input is via an encoder with the output of the length register of the field being processed, and the third input and output are respectively with the output and input of the i-ro register of control transfer conditions, register output liny connected to the input operands Arithmetic logacheskogo block and second block inlet comparing results arithmetic-logical operations. M registers of the mask and the switch of the mask are entered into the device, the first input of the i-ro block forming the generalized signs of arithmetic logic operations is additionally connected to the i-th input of the first group of inputs of the mask switch and the input of the i-ro regaster of signs, the fourth input - with the switch output masks, the output of the 1st register of attributes is connected to the 1st input of the second group of inputs of the mask switch. In addition, the block forming the generalized signs of arithmetic-logical operations contains a group of elements AND, a group of elements OR, an element AND, an element OR, and two groups of elements NOT, and the group of inputs of the element OR is connected to the outputs of the corresponding elements AND group, the first, second and third inputs which are connected to the discharge of the first, second and fourth inputs of the block, respectively, the group of inputs of the element I is connected to the corresponding outputs of the elements of the OR group, the first inputs to which are connected to the corresponding rails to the first group's first input, the second through the corresponding elements of the first group to the corresponding bit buses of the second input of the block, and the third inputs through the corresponding NOT elements of the second group to the corresponding bit of the fourth input of the block, the input of the AND element and the input of the OR element to the corresponding values of the third input of the block, the outputs of the AND and OR elements are the corresponding output of the block. Introduction of generalized features of arithmetic logic operations, an operand length register and an encoder into the device block, which converts the code contained in the field length register into a unitary code, and the unitary code is the code containing the number of further units located equal to the number of operands in the field being processed allows to reduce the number of operations for analyzing an array of operands. The introduction of feature registers and mask switches allows you to prohibit the use of features of some of the results of operations when generating generic features. In turn, the introduction of a block for forming generalized attributes of arithmetic-logical operations allows generating generalized signs of the type; all signs of the results of operations are equal to one, even if one sign is equal to one. FIG. 1 shows a block diagram of the proposed device; in fig. 2 - functional block diagram of the formation of generalized features of arithmetic logic operations. The device contains an arithmetic logic unit (A L B) 1, a block 2 comparing the results of arithmetic logic operations, a register 3 of the length of the field to be processed, a register 4 of the transmission conditions of the utility, a block 5 of generalized signs of arithmetic logic operations, 6 of the length of operands. the encoder 7 of the code contained in register 3 of the length of the processed pop into the unitary code, registers of 8 features and switch 9, in addition, the first input 10 of block 5, inputs 11 and 12 respectively of the first and second groups of inputs of the switch 9, the fourth 13, the second 14 and the third 15 inputs of block 5. Block 5 of forming generalized features of arithmetic logic operations can be performed in a time-varying manner. In particular, to form generalized attributes of type, all signs of the results of operations are equal to one, at least one characteristic is equal to unit, block 5 contains elements AND 16 groups, element AND 17, elements OR 18 groups, element OR 19, elements NOT first 20 and second 21 groups. The device works as follows. ALB 1 for CBP1, a clock cycle performs a given operation on a certain fixed number of bits of the processed pl, which is an array of operands and stored, for example, in the internal memory of the ALB. These bits, depending on the length of the operands specified by register 6, can be either a few array operands, or some of the bits of one operand. Respectively, in one cycle of operation of the ALB 1, the results of processing several operands will be obtained, or in several cycles, the result of processing one operand. The results obtained in ALB 1 are sent to block 2, which produces a group of prints (for example, the operands of the raina are not equal, one operand is greater, not more, less, not less than the other) for each result of the operation.: Signs of the results of operations from the outputs of the block 2 enters the corresponding blocks 5 via inputs 10. Blocks 5 form features that are generalized over the entire array of operation results. If the array of operands is processed in several cycles, then the condition register 4 can be used to store partially formed generalized features. In this case, from the beginning of each processing cycle, the new signs arriving at block 5 via inputs 10 are converted, taking into account the results of the conversion for the previous steps of this operation, entering block 5 through inputs 15 For devices, in which the signs of the entire array Operands arrive in blocks 5 in one clock cycle; inputs 15 are not used. In the general case, the length of the processed field in a register in register 3 is not equal and is not a multiple of the number of bits processed by the ALB 1 per cycle. Therefore, in the last processing cycle, a part of the signs may be related to the results of operations on operands located outside the field being processed 56 To eliminate the effect of these characteristics on the formation of generalized features, the generator 7 in each cycle generates the resolution signals that go to blocks 5 at the inputs 14. In addition, the signs of the result of processing some elements of the field can be eliminated from the formarovash {generalized signs with the help of the mask signals received in the blocks 5 through the inputs 13. The mask can be one of the signs generated in the current operating system, or the contents of one of the registers 8, which may be, for example, signs of previous operations. The mask information is chosen for the mask by the switch 9. Generalized 1e, the characteristics are stored in register 4. Thus, the device allows you to {form the generalized characteristics of the arrays of processing results of operands) at variable lengths as operandop and n arrays of operands, and indications of the processing results of individual operands may be masked. The formation of generalized features can be accomplished in various ways. Block 5 (Fig, 2) is designed for O1 P1rowat1 o6o6niemn ix. signs of type signs of all results are equal to (all units). the sign of at least one result is equal to one (at least one edlnitsa). The generic attribute all units are formed by the element AND 17, to which the inputs 23 from the inputs 10 of the block 5 through the elements OR 18 receive the signs, B1) 1 worked in the current clock cycle, and the inputs 25 partially generated the prizdak from the register of 4 conditions. Generalized, although 6bi one e; 1, the elements OR 19 are formed, to which signs 22 from inputs 10 through elements 16 enter inputs generated in the xeKyuieM cycle, and input 24 receives partially a character from register 4. On inputs 13 Block 5 receives a mask that prevents the passage of single value signs through the elements AND 16 fipH of the formation of a sign, although one unit also records the same value for the sign of all the items through the elements HE 21 and OR 18 - with a bullet of the masking signal. The blocking signals supplied to the inputs of block 14 are paBimi units for those signs that relate to the field being processed and zeroes for the rest of the signs. Outside the field being processed, they prohibit the participation of unit n 1X values of attributes (element 16) in the formation of the trait at least one unit and the formation of unit values for the attribute all units (elements 20 and or 18).

Thus, the proposed device provides the formation of generalized signs of all units, at least one unit with a variable length of the field being processed and the possibility of masking the processing characteristics of individual operands, which reduces the time needed to solve problems of a particular class compared to the time spent by a known device, and thereby improving system performance.

Claims (3)

1. An information processing device containing an arithmetic logic unit, the output of which is connected to the first input of the comparison unit of the results of arithmetic logic operations, a register of the length of the field being processed and M control registers of transmission conditions, characterized in that he entered the register length of the operands. M blocks of forming generalized signs of arithmetic logic operations and an encoder, the first input of the i-ro block forming generalized signs of arithmetic operations (i 1, M) connected to the i-th output of the block comparing the results of arithmetic logic operations, the second input through an encoder with output The register of the diggin of the field to be processed, and the third input and output, respectively, with the upstream input and the input of the i-ro register of control transfer conditions, the output pe, and the gist of the length of the operands are connected to the input of the arithmetic logic unit and the second input. home block comparing the results of arithmetic operations. 2. The device according to claim 1, characterized in that M registers of attributes and the switch of the mask are entered into it, moreover the first 68- 658 The new input of the i-ro block forming the generalized features of arithmetic logic operations is additionally connected to the i-th input of the first group of inputs of the mask switch and the input 5 i-ro register of attributes, the fourth input - with the output of the mask switch, the output of the 1st register of attributes is connected to the 1st input of the second group of inputs of the mask switch. 3. The device according to claim 2, of which there is a group of elements AND, a group of elements OR, an element And, an element OR, and two groups of elements NOT, moreover, the group of inputs of the element 15 OR is connected to the outputs of the corresponding, AND elements of the group, the first, second and third inputs of which are connected to the bit buses of the first, second and fourth inputs of the block, respectively, the group of inputs of the AND element 20 is connected to the corresponding outputs of the Ele. OR groups, the first inputs of which are connected to the corresponding bits of the first input of the block, the second through the corresponding elements are NOT the first group 25 to the corresponding bit buses of the second input of the block, and the third inputs through the corresponding NOT elements of the second group to the corresponding bit buses of the fourth input of the block, the input of the AND element and the input of the OR 2Q element are connected to the corresponding buses of the third input of the block, the outputs of the AND and OR elements the respective output tires of the unit. Sources of information taken into account in the examination 35 1. US patent number 3949376, CL. 340-172.5, published 1976. 2. Design of superfast systems Stret. M., Mir, 1965. 3.Flores A. Organization Computing 40 machines. M., Mir, 1972 (prototype)