SU862144A1 - Microprogram processor with checking - Google Patents

Description

{54) FIRMWARE PROCESSES WITH CONTROL

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The microprocessor processor with a kbit role belongs to the field of digital computing and can be used in a computer with firmware control.

A microprocessor processor with a control is known, which contains an operadig block, registers of microinstructions and the microcommands proper / microinstructions memory block, a qpaanan node, a flip-flop trigger and logic elements AND, OR, NOT

The disadvantage of the device is low reliability of operation and low efficiency of control.

The closest in technical essence and the achieved effect of the known devices to the invention. is a microprogrammed processor containing an operative block, a microinstruction memory block, the register "1cro. commands, two address registers, an operation code register, a comparison block, a commit trigger, ten AND elements, four OR elements, two NOT elements, a delay element. Shdhod operation code-operational block is connected to the input of the operation code register, the output of which is connected to the first input of the first, element And, the second input

which is connected with the output of the start of the operational unit and the first input of the toric element OR, the output of the first element. And connected to

 The first input is the first register of the address, the second input of which is connected to the BUxoscnit of the second element I, and - C the overweight of the block pa111 МЯ7И, the third and fourth elements. B1sbd of the third element I is connected to the reading output of microcommands of the operocyclic flea, the second input of the block of paу01ti microcommands, and also through the delay element with

1 the first input of the p element and. & lsod of the third element And is connected to the neipf at the input of the second "chaeogistra. The output of the microcoma1 memory unit | d is connected to the register input

2 ith commands, the output of the crocs is connected, with the first input of the operating room O Roo address output - with the second input of the operating unit and the first input of the sfottoro element And, the output

25 logical conditions - with the first input swKMBHta I. the second input of the second eledlev and through the first element BE connect it with the output of the first element Wra, "the second input of which is connected

for vt yeojUfXt at the end of the operation of the operation unit, the first input of the seventh element I, the third input of the first address register, the second input of the second address register, the output of which is connected to the second input of the fifth element I. The second input of the seventh element I is connected to the address output of the register microinstructions, the output is from the first input of the second OR element, the output of which is connected to the first input of the comparison unit. The second input of the second OR element is connected to the output of the sixth AND element, the second input of which is connected to the output of the delay element and the first input of the third OR element, the second input of which is connected to the output of the first OR element and the second input of the fourth AND element, the output of which is connected to the third the input of the second element OR. The first input of the eighth AND element is connected to the output of the operation code register, and the output to the first input of the fourth OR element, the second input of which is connected to the output of the fifth AND element, and the output to the second input of the comparison unit, the third input of which is connected to the output The second input is And, the first input of which is connected to the output of the third element OR. The second input of the ninth element AND through the second element is NOT connected to the output of the regis-pp microinstruction label and the first input of the tenth element I, the second input of which is connected to the output of the logical conditions of the microinstruction register, and the third input - to the output of the logical conditions of the operation unit, the third input of which is connected to the output of the latching trigger, the input of which is connected to the output of the comparison unit. The output of the tenth element I is connected to the fourth input of the first register of the address G2. The drawback of the device is the low efficiency of monitoring the compliance of the executed firmware with the firmware whose code is recorded in the operation code register. The aim of the invention is to increase the speed of control and reliability of the operation of the microprogrammed processor. This goal is achieved by the fact that the trigger trigger, modulo two, eleventh and twelfth elements AND, the fifth element OR are additionally introduced into the microprogrammed processor with control. The first input of the modulo two adder is connected to the output of the logic conditions of the operating unit, the output is connected to the fourth input of the second OR element, the second input of the adder is modulated to the output of one XI-XIII element AND, the first input of which is connected to the output of the logical conditions of the microinstruction register, the second input of the eleventh And element with the output of the twelfth And element, the fourth input of the comparison unit and the first input of the fifth OR element, the second input of which is connected to the output of the first OR element, and the output to the second input of the eighth ele element I. The first input of the twelfth element I is connected to the output of the second element NOT, the second input is connected to the single output of the trigger of the sign, the single input of which is connected to the output of the register of microinstructions. The zero input of the trigger of the sign is connected to the output of the ninth And element, and the zero output to the third inputs of the fifth and sixth And elements, the third input of the twelfth And element is connected to the output of the delay element. The essence of the invention consists in increasing the control efficiency by increasing the number of checks of the compliance of the executed microprogram with the specified operation code, as well as in increasing the reliability of operation by controlling the correctness of the branch of the NgiK program. At the same time, the control of the correspondence of the executed firmware to the specified code of operation and the control of the correctness of the execution of the branches in the microprogram are carried out simultaneously by the general means of verification. However, time control is implemented after reading the first microcommand following the next branch and in the microprogram. This makes it possible to increase the efficiency of monitoring the correspondence of a given operation code to an L4 and D program, and bring it up to the average time between branches, as well as increase the reliability of operation by organizing control branches. The drawing shows a functional diagram of a microprogrammed processor with control. The following notation is used in the drawing: operational unit 1, outputs of logical conditions, operation start, operation end, operation code and microcommand reading 2-6, respectively, the first element OR 7, and the operation code register 8, the first element is NOT 9, the first element is AND 10 , the second element And 11, the tenth element And 12, the first register of the address 13, the block pg1M of micro-commands 14, the register of micro-commands 15 with the address field 16, the micro-commands 17, logical conditions 18, marks 19, the seventh element And 20, the second element NOT 21, the eleventh element And 22, the modulo two 23, trig The sign 24, the twelfth element And 25, the delay element 26, the sixth element And 27, the second element OR 28, the third element And 29, the second register address 30, the loop element And 31, the four-element element AND 32, the fourth element OR 33, the third element OR . 34j, the ninth element AND 35, the fifth element OR 36, the eighth element AND 37, the latch trigger 38, the block compared to the NIN 39, the first - the fourth inputs 4043 of the comparison block, respectively

output 44 of the comparison unit.

The first register of address 13 is intended to store the address of the next micro-command during the execution of the current micro-command.

The second register of address 30 is designed to store the code of the address received from the first register of address 13 for the time of reading the microcommand from the memory of microcommand 14.

The microprocessor processor works in the following way.

The execution of each command is divided into two cycles: the cycle of selecting the command and the cycle of its execution in accordance with the operation code. The first cycle is common to all commands, while the execution cycle consists of various firmware for various commands.

At the end of the sampling cycle, the command and address conversions the operation code goes to the operation code register 8, and the operation unit 1 generates a signal to start the operation. On this signal, the operation code enters through the first element AND 10 in the first address register 13.

The validity of the operation code entry in the address register 13 is monitored by comparing its contents with the contents of the operation code register 8 by the operation start signal from the operation unit 1.

This signal Gshres of the first microcommand from the output of the first register of address 13 enters through the fourth element AND 32 to the third input of the second element OR 28 and further to the first input 40 of the comparison unit 39.

Simultaneously, the start of the operation from the output of the first element OR 7 goes through the fifth element OR 36 to the second input of the eighth element AND 37, allowing the operation code from the output of the kodg register of operation 8 to pass through the fourth element OR 33 to the second input of the comparison block 39. Further these codes are compared according to the start of operation signal, which comes from the output of the first element OR 7 through the third element OR 34 and the open ninth element AND 35 to the third input 42 of the comparison block 39. If the codes do not match then the output 44 of the comparison block audio signal 39 is generated, which is supplied to the trigger input of fixing SRB dgshneyshuyu 38 and prohibits operation of the operation unit 1. If the codes match, the operation proceeds processor. At the readout output of microcommands 6 of the operation unit 1, a signal is generated by which the microcommand is read at the corresponding address from the memory block of macro commands 14. The same signal goes to the second input of the third element And 29, and the microcommand address is written to the second address register 30. Through the time f (the read time of one microcommand from the microcommand memory block 14) in the address

0 the field 16 of the register of microinstructions 15 forks the address of the next microcommand that arrives at the first input of the second element 11, opened by the element NOT 9. (during execution

5 microprograms of the signal at the start and end of the operation and the output of the element OR 7 are absent), and to the second input of the operation unit 1. Pass through the element 11, address

0 is written to the first register of address 13.

At the first input of the operation unit 1, the operation part of the readable micro-command is received from the field of micro-commands 17 of the register of micro-commands 15.

five

From the logical conditions of 18 pe of the gist of kmcrospectives 15, the address of the executable microcommand is read, which is fed to the first input of the sixth element And 27. At this time,

0 its second input. A signal comes from the reading output 1 "| of the co-operations 6 through the delay element 26, and the third input receives a single signal from the zero output of the trigger of sign 24. Address

5 of the executed microcommand through the second element OR 28 enters the first input 40 of the comparison unit 39. After the address of the executed microcommand is written into the second register of the address 30

0 through time Tj, the first input of the fifth element AND 31 will receive a signal allowing the transfer of the address recorded in the second address register to the second input of the fourth element OR 33. Address transmission is possible, since the third input of the fifth element AND 31 receives a single signal from zero output of trigger 24

Through the fourth element OR 33

0, the address recorded in the second register of address 30 is fed to the second input 41 of the compare block 39.

From the output of the delay element 26 cherbe BpeMsfj, the mic5 rocomand read signal is fed to the first input of the ninth element AND 35 through the third element OR 34, the second input of which receives the enabling signal from the output of label 19 of the microcircuit register 15. The formed signal from the output of the ninth element And 35 is fed to the third input 42 of the comparison block 39. At the same time, the correctness of the read of the microcommand is controlled by comparing the incoming

five

va entry codes. Depending on the comparison of the address codes, the processor's operation is similar to that described above. In the future, when reading irokomando from the microcommand memory unit 14, the control of the order and accuracy of their reading is carried out in a similar way.

When executing a microcommand, branching in the field of logical conditions. 18 of the register of microcommands 15, the code of the logical condition being verified is recorded. It arrives at the second input of the tenth element I 12, at its first input it receives a single value from the output of label 19 of the register of microcommands 15, and the third - the value of the checked logical condition. As a result, the next Microcommand address is formed (modified). A single signal from the output of the Mark 19 of the microinstructions register 15, the trigger of the sign 24 is set to the single state, and at its single output appears the enabling signal, which is fed to the second input of the twelfth element 25.

There is no comparison of the values of the codes recorded in the field of logical conditions 18 of the register of microinstructions 15 and the contents of the second register of address 30, since the second input of the ninth And 35 element receives the zero value from the output of the label 19 of the register of microcommands 15 and there is no signal for resolution comparison . The third input of the sixth element And 27 receives the zero signal from the zero output of the trigger of sign 24, prohibiting the transmission of information to the comparison block 39. After reading the first microcommand after branch 1 and in the field 19 of the register of microcommands 15, a zero signal appears that is inverted by the second element NOT 21 and arrives at the first input of the Twelfth element I 25, to the second input of which a single signal is received from the output of the trigger of the sign 24 and from the reading output of the microcommands 6. At the output, a permission signal is generated, which goes to The second input is the eleventh element AND 22. The first input element AND 22 receives the control sign recorded in the field of logical conditions 18 of the first micro-command after branching. The control code is the operation code modified by the value of the logical condition being checked. The code modified in this way arrives at the second input of the modulo two 23, the first input of which receives the value of the logical condition to be carried out. At the output of the modulo two 23, the result is the actual value of the operation code, which is fed to the fourth input of the second element OR 28 and then to the first input of the iO comparison block 39.

The resolution signal from the output of the twelfth element And 25 is also fed to the first input of the fifth element OR 36 and from its output to the second input of the eighth element And 37. B)

the actual value of the operation code from the output of the register of the operation code 8 through the fourth, the OR element 33 is fed to the second input 41 of the compare 39 block. At the same time, its fourth input 43 receives a signal to allow comparison of the codes from the output of the And 35, and then the signal from the output of the element 35 and the trigger of the sign 24 is set to zero. Further, the processor is similar to that described above.

Simultaneously with the control of the correspondence of the executed firmware to the specified code of operation, the control of the correctness of the branches is carried out.

If the nOJby4eH transition is erroneous as a result of the summation of the checkpoint and the value of the logical condition being checked, the code does not match the required operation code and the output 44 of the comparison unit 39 generates a failure signal.

In this case, the processor implements the remaining part of the microprogram by checking the correctness of the reading and order of the microinstructions and verifying that the microinstructions belong to the given microprogram according to the algorithms described above.

When reading the last microcommand, the address of the read microcommand is recorded in the field of logical conditions 18 of the register of the glcro. Commands 15, and the code of the operation being performed is written in the address field 16. According to the read signal delayed by the delay element 26, the comparison unit 39, similarly to that described above, compares the codes received from the field of the logical conditions 18 of the microcommand register 15 and the second address register 30.

Claims (2)

1. Author's certificate of the USSR 512471, cl. G 06 F 15/00, G 06 F 9/16, 1975. 2. USSR author's certificate on the certificate 2756704 / 18-24, cl. G 06 F 15/20, G 06 F 11/00, 1978 (prototype). NX i N H ± 1  jfc: W fe5 feb H r k SHL "S4 H