SU860072A1 - Device for address forming - Google Patents

Description

one

The invention relates to computing and can be used in the construction of devices for the formation of addresses in the central processes of digital computers.

An address shaper is known that contains the initial data and scan sector memory blocks, odd and even frame random access memory blocks, the first and second switches, an adder, an address counter, a control unit, a correction sensor, and a converter l.

The disadvantage of this address builder is the complexity of programming.

It is also known that the address device of a digital computer, which contains the register of operands, accumulate blocks, the register of block numbers; code register, OR elements, reference block, AND elements, counter 2.

The drawback of the device is a large amount of hardware and programming complexity.

The closest to the proposed technical entity is an address generation device comprising a command address register, a memory data register, a command counter, a number address register, a register, and switches 3.

The disadvantage of this device lies in its limited functionality.

The purpose of the invention is to expand the functionality of the implementation of the data processing shown.

The goal is achieved by the fact that in an addressing device, containing an instruction counter, an instruction address register, a register, first and second switches, the first input of the first switch is connected to the input of a hardware device, an address setting, the second input of the first switch is connected to the first output of the device and the register output, the input of which is connected to the first information input of the device, the counting input of the command counter is connected to the counting input of the device, the input of the register of the address of the number is connected to the second information the device’s input and the first input of the second switch, the output of the first switch is connected to the address output of the device and to the information input of the command counter, the output of which is connected to the second

the input of the second switch, the output of which is connected to the input of the command address register, the output of which is connected to the second output of the device and the third input of the first switch, the output of the number address register is connected to the quarter input of the first switch.

The drawing shows a block diagram of an apparatus for generating an address.

The device contains a command counter 1, a command address register 2, a number address register 3, a register 4, the first switch 5, the second switch 6, the address output 7, the count input 8, the first output 9, the first information input 10, the second output 11, the second information input 12 / input 13 hardware address setting.

The device works as follows.

In the command word sampling mode, an address code is output from the output of the register 2 command addresses to the output of the switch 5. The address code of the command is sent to the address input b of the device and to the input of the counter 1 command, to the counting input of which, from input 8, a code equal to one is given if the command word occupies n bits in memory and equals two if the command word takes 2 n bits . Then, the increased command address is written to register 2 command addresses via switch 6 from the output of command counter 1. In operand access mode, the operand address of the operand recorded after registering the device’s input address number 12 on the device, from register output 3 of the address via the switch 5 is supplied to the address output 7 of the device. In the interrupt exit mode, at the input 13 of the hardware address setting, a code is generated that is equal to the address of the first word of the old MSP program state word for the corresponding interrupt class, in which the contents of the command counter are stored. This address code through the switch 5 is fed to the address output 7 of the device and the input of the counter 1 commands. At the same time the contents of the register 2 addresses of commands through the exit

11 devices are fed to a memory device. After memorizing the first word of the old MSD, the command address register 2 is written to the increased value of the MSB address, then the next values of the MSP addresses of this class of interrupt when changing the MSP to the address output 7 of the device and after increasing are written to the register 2 command addresses. The address of the interrupt processing subroutine when selecting a new MTP is selected last, while it is through the input

The 12 devices and the switch 6 are fed to the input of the register 2 of the address of the commands and written into it, after which

The interrupt routine is executed. When completing commands for switching the address of the transitions to the register 2, the addresses of the commands are given from the input 12 of the device.

In the store organization mode of processing an array of information, the address of the first word of the array is recorded on register 4 from input 10 of the device. When sampling the first or next word of the array, its address code is fed from the output of register 4 through the switch 5 to the address output 7 of the device. At the same time, the address code from the output of register 4 is fed to output 9 of the device and, after increasing in the processor, returns to register 4 via input 10 of the device. It should be noted that the given structure of the device allows arranging the arrays of numbers in case of the store organization of their processing in the middle of the program; array, then when it is sampled, its address arriving at address output 7 of the device and the input of the counter 1 command. After incrementing at counter 1, the command is written to register 2 of the commed address via switch b from the output tchika 1 teams.

Thus, the proposed device is operable in the modes inherent in the modes of operation of the known and also allows the store data processing mode to be provided, and the information arrays can be located in the program itself, which allows to expand the possibilities of organizing transitions in the program.

Claims (3)

1. Author's certificate of the USSR 489106, cl. G 06 F 9/00, 1972. 2. Authors certificate of the USSR 401997, cl. G About F 9/00, G 11 C 7/00, 1971. 3. Hasson S. Firmware management. Issue 2, M., Mir, 1974, fig. 8.7 (prototype). AND (. f ten at 7