SU857985A1 - Probabilistic simulating device - Google Patents

Description

one

The invention relates to computing and can be used in the construction of simulation equipment for the study of structurally complex systems.

A random pulse generator is known, in which random pulse streams with known probability characteristics are converted into random pulse sequences with the required distributions of pulse stream parameters. This generator contains sensors for punch random pulse flows, blocks for random tests, blocks for analyzing the results of random tests, blocks for converting random variables to random numbers or to random values of the parameters of pulsed flows Cl3.

The disadvantages of this generator are that it does not allow the formation of Markov processes with a finite set of states and investigate the connection between probabilistic graphs.

A device for determining the NIN of the connectivity characteristics of a probabilistic graph, connected by an electronic digital computer and comprising a vertex exciter, a code bus excitation unit, an analysis unit and a pulse generator G23.

The disadvantage of this device is that it can only be used to study the connectivity of a probable graph. Sequence modeling

10 random numbers with hung probability characteristics and Markov random processes on it are impossible. In addition, the use of digital computers to form random

15 states of the vertices and arcs of the graph and for outputting the obtained values to the vertex excitation units and the code busses reduces the performance of the system as a whole.

20

The closest technical solution to the present invention is a device for probabilistic modeling, containing serially connected input block,

25 executed on sensors of a stream of random pulses with adjustable intensities, a block of AND diagrams, an encoder, a register number of the matching circuit, an OR circuit, a pulse generator, and

30 counter.

The device generates random events as a result of random tests involving simultaneous optics on the common input of the matching circuit block and setting in the register a code corresponding to the match circuit number through which the first pulse of the input block sensors passed since the test began. The pulse generator and the counter convert the resulting random number into a random time interval,

The disadvantage of this device is that it does not allow - form Markov processes with a finite set of states and investigate the connectivity of probability graphs.

The purpose of the invention is the expansion of functional possibilities by forming homogeneous Markov chains with a finite set of states for studying the connection of probability graphs, determining all possible simple chains in a graph with given probabilities of arcs and lines.

To achieve this goal, a probabilistic modeling device contains an input block, the first group of outputs of which is connected to the first group of inputs of the block of elements AND, respectively, the outputs of which through the encoder are connected to the inputs of OR, the elements of OR and the inputs of the first shift register the output of the device and connected to the input of the input block, entered the control unit, the element AND, the group of elements OR, the second shift register, whose inputs are connected to the first group of outputs of the input block, respectively, the second group of output terminals is connected to the first inputs of the group of elements OR, the second inputs of which are combined with the second group of inputs of the AND block and connected to the outputs of the second shift register, the Reset input of which is combined with the Reset input of the first shift register and connected to the first output of the control unit, the second and third outputs of which are connected to the inputs of the shift of the second and first shift registers, respectively, the fourth output of the control unit is connected to the third group of inputs of the block of elements And, the outputs of the group of elements Combus OR is connected to the inputs of the AND element, whose OUT04 is connected to the first input of the control unit, the second input of which is connected to the output of the OR element, the third and fourth inputs of the control unit are respectively the first and second inputs of the device.

In addition, the control unit contains a trigger, four AND elements, four OR elements, three delay elements and two impulse drivers.

The first input of the control unit is connected to the first S-input of the trigger, the second S-input of which through the first delay element is connected to the output of the first OR element, the first input of which is combined with the R-input of the trigger and is the second input of the control unit, the third input which is connected to the first input of the first element of the first input of the second element OR, the output of which is connected to the third S-input of the trigger and through the first pulse shaper is connected to the first input of the control unit and to the input of the second delay element, output to torogo

5 is connected to the second entrance of the first element AND, the output of which is connected to the first input of the third element OR, the second input of which is connected to the output of the second element AND, the first

Q input is through the third element. the delay is combined with its second input and is connected to the first input of the fourth OR element, the output of which is the second output of the control unit, the third output of which is connected to the output of the third OR element and to the second input of the first OR element, the fourth output of the control unit is connected to the output of the trigger and with the first input of the third element

0 and whose output is connected to the second input of the fourth OR element, the fourth input of the control unit is connected to the second inputs of the second OR element, the third AND element

5 and with the first input of the fourth element And, the second input of which is connected to the output of the first pulse shaper, the output of the fourth element And through the second pulse shaper is connected to the input of the third delay element. .

FIG. 1 shows a block diagram of the device J in FIG. 2; it is a functional diagram of the control unit; in fig. 3 and FIG. 4 - timing charts of the signals at the outputs of the control unit.

The device contains an AND 1 block, an encoder 2, a first shift register 3, an OR 4 element, a second shift register 5, a group of OR b elements, an AND 7 element, a control block 8, an input block 9. Block 1 contains three-input elements AND 10, block 6 two-input elements OR 11, block

5 9 inputs — 12 memory modules, 13 random pulse current generators, OR-NOT 14 elements, terminals 15.

Control unit 8 is executed on trigger 16 with three combined input logic AND inputs S and input R, elements AND 17, 18, 19 and 20, elements OR 21, 22, 23 and 24, elements 25, 26 and 27 delays, drivers 28 and 29 pulses. The control unit 8 also has control terminals 30 and 31. Consider the functional purpose of the structural components of the device. Shift register 3 is used to store, during the simulation, the i number of the last vertex of the graph passed to the data, moreover, clause. To set the number of the initial vertex of the graph or the initial state of the Markov process, serve as terminals 15 connected to the controlled inputs of the initial register 3 shift, recording the number of vertices from which occurs by the signal of the ultrasonic unit 8, arriving at the second control input of the shift register 3. To change the state of the 3 shift register in the model simulation process, the write inputs connected to the corresponding outputs of the encoder 2 are used. In addition, the register has the first input of setting to zero state. The shift register 5 has the first input of the installation to the zero state, the control inputs of the installation to the single state for each register bit, the recording of information from which is allowed in the presence of the control unit 8 signal Y2 on the second control input of the shift register 5 and on the rising edges of the signals with the output of block 9 input. The input unit 9 generates n random pulse flows with intensities j, where j is the flow number, k is the current vertex number or the state of the Markov process, which enters the input of block 9. Thus, each state k of the shift register 3 corresponds to certain intensities Generators block 9 input. If for some j at a given K the intensity is H 0, then at the J-OM the additional output of the input block 9 produces a signal arriving at the input of the corresponding circuit OR block 11 The structure of the random test in the proposed device is not different from the test structure in the known device and consists in simultaneously unlocking the elements And 10 of block 1 followed by fixing in shift register 3 a number corresponding to the number of the element 10 And block 1 through which the first random impulse from the outputs of the block OK 9 input. The dependence of the probability distribution of the state of the shift register 3 after random testing on the values of the flow intensities at the outputs of block 9 may be different. In particular, if block 9 generates Poisson flows with intensity MJs, the number of flows, then the probability that c. the result of the test in register 3 will be set to number t, which is defined as: & lg P x Km. The structure of input block 9 may be different. For example, the option shown in Fig. 1 is selected. A number from register 3 is fed to the combined address inputs of modules 12, the output of each of which is connected to the intensity control input of the corresponding generator 13 random impulse streams and the input of the corresponding element OR NOT 14, output which is one of the additional outputs of the input block 9, and the outputs of the generator 13 are the outputs 1 and of the block 9. Before starting work, the AKJ values are written to the memory modules 12 for controlling the intensities of the LJ KJ generator 13 s, and j indicates the number of the memory module 12, and the address k of the cell in the module where, n; , n. When simulated forbidden (unreliable) vertices, with, n, graph arcs or states of a Markov process are simulated. Since 0 corresponds to, when reading the zero code from module 12, the corresponding OR-NOT 14 element is triggered. When a resolution signal M is applied to terminal 10, corresponding to the case of the Markov random process simulation, a sequence of signals is generated (Fig. 3). The element OR 22 (t) is triggered, the driver 28 generates a single pulse U1, of duration tjg. After the delay time of the signal With the element 26, the element And 19 and OR 24 are triggered, an ultrasonic signal (tQ) is produced. Trigger element OR 21 and after the delay time TIJJ element 25 sets the trigger 16 (tj). On the SI pulse (tj.), The trigger 16 is reset, the element OR 21, the element 25, the trigger 16 is again triggered after time t ,. is set and the cycle repeats. The device is operated either until the JJ- signal is reset, or until a signal appears at the first input of the control unit 8 prohibiting the trigger 16 installation. When the enabling signal G, corresponding to the probability graph simulation, is applied to terminal 31, the unit 8 generates a signal sequence (FIG. .four). The elements of OR 22 are triggered, the former 28 is generated, the Y1 (t) signal is generated. At the time tg, the Y1 signal ends, the AND 18 element is triggered, and the imaging unit 29 is started, generating a signal with a certain

specified duration Triggered element OR 23, produced by Y2. At time ti, termination Y2, the elements AND 2O; -OR 24, are triggered, produced during the interval defined by the delay circuit 27, the ultrasonic signal. The elements OR 21, Strums 25 are triggered, the trigger 16 is set, Y4 (t4.) Is generated. And 17, OR 23 elements are triggered, Y2 is generated. According to the SI, the tg-trigger 16, and at the same time both the signals U4 and U2, are reset, similar to the one that is before, again set, etc. The device is stopped either by resetting the signal G, or by a signal arriving at the first input of the control unit 8.

Consider the operation of the device in the formation of homogeneous Markov chains with a finite set of states. The terminal 30 of the control unit 8 receives a signal d, through which the unit 8 forms a sequence of signals, shown in FIG. 3

On signal U1, registers 3 and 5 are set to the zero state. Since Y2 is not generated in this mode, register 5 is permanently set to zero and there are low levels at its outputs, which are fed to the inverse second inputs of elements And 10 of block 1.

The signal KS in the register 3 records the initial state ko of the Markov process of the terminals 15. From the cells with the address kQ of the modules 12 of the memory of block 9, codes are read that adjust the generators 13 to the intensities ((oj corresponding to the process transition probabilities from the state kp j state

o The signal U4 allows the passage of pulses with the output of the generators 13 through the block 1 of the elements And 10, and thus begins the random test. The first pulse passed through block 1 of input block 9 passes through encoder 2, sets in register 3 the number k of the next state of the Markov process and simultaneously arrives at the element OR 4. The output signal C of the element OR 4 resets the signal U4 in block 8 of control, resulting in elements 10 are closed and terminated randomly. During the interval fjj, the codes AIC.J are read from the cells with the address k of the modudi 12 memory, I1 intensity stops, after which the block 8 again generates the signal Y4, the next random test starts, etc.

The formation of a Markov process stops when a given state of the process is reached by resetting the GA signal, or if the next state k has zero transition probabilities P.j, and therefore.

and zero AK. . At. This is triggered by the OR-PE 14, OR 11, and 7 elements, the output of which stops the operation of the control unit 8.

Consider the operation of the device in the study of the connectivity of probability graphs. The timing diagram of the signals generated by block 8 in this mode when the signal G arrives at the block terminal 31 is shown in FIG. four.

On signal U1, registers 3 and 5 are set to the zero state. From the zero cells of the modules 12 of the memory of block 9, the codes Ad. Are read,. Block 8 generates a signal Y2 with a duration of Tag / during which random pulses from the outputs of the generators 13 can set the triggers of the register 5 to one state. By changing the parameters A (JJ and Cge of the duration of the Y2 signal, it is possible to regulate widely the probabilities of setting the triggers of register 5, and consequently, the probabilities of the existence (reliability) of graph vertices.

Suppose that in register 5, the portions of the terminations U2 are set to 1, 3, and 12th, which corresponds to nonexistent 1, 3, and 12th vertices of the graph. Then, in block 1, elements AND 10 with numbers 1, 3 and 12 will always be closed. Consequently, in register 3 numbers 1, 3 and 12 will never be set, which eliminates the paths through these vertices.

By the signal of US, the register 3 from busses 15 is written down the number k with the initial vertex of the graph. From the modules 12, codes A) t, j- are read out, the intensities Xkoj are set. The signals U2 and U4 are produced. A random test begins, however, the passage of pulses from the outputs of the generators 13 is allowed only through those circuits and 10, on the inverse second inputs of which there is a low potential.

The first impulse of block 9 passed through block 1 passes through encoder 2, sets number 3 in register 3 as the next vertex of the graph, sets register bit in unit 5, enters the input of the element OR 4, the output signal of which SI resets signals 8 in block 8 , Y2, thereby terminating the test. After the interval Jnj, required for reconfiguring the generators 13, Y2 and Y4 are again generated, random testing is repeated. However, now the circuit with number k has been added to {10 closed elements AND 10, thus preventing the repeated setting in register 3 of number k, which prevents the passage of the path on the graph through the same vertex twice.

Claims (3)

1. USSR author's certificate No. 504196, cl. G 06 F 1/02, 1974. 2. USSR author's certificate №433504, cl. e 06 G 7/48, 1972. 3. USSR author's certificate number 3443431, cl. G 06 G 1/02, 1970 (prototype). FIG. 2