SU857983A1 - Random number generator - Google Patents

Description

(54) GENERATOR OF RANDOM NUMBERS

one

The invention relates to computer technology, in particular for the implementation of a Monte-Carlo method on a computer, and also for statistical modeling of complex systems, solving problems of the theory of reliability, etc.

The random numbers generated by the device are interpreted as random events that can occur with corresponding probabilities in the complex system being modeled.

A random number generator with predetermined distribution laws is known. It uses as the input data the probabilities of the occurrence of zeros and ones in each bit of the random number generated, coming from the Ul computer.

The generator provides generated 1 | e random numbers with given distribution laws. However, the use of random probabilities leads both to a complication of the algorithms for calculating them on a computer, and the process of generating random numbers in the device itself, and, consequently, to an increase in the necessary equipment.

The closest technical solution to the present invention

is a random number generator containing a primary source of uniformly distributed random numbers, a clock generator, a comparison unit, a memory unit, a counter C2j.

The disadvantage of the known generator is that it does not allow modeling the problems of the theory of reliability.

The purpose of the invention is to expand the functionality of the generator by forming a random stream of random numbers representing

15 flow of failures with indication of the number of the failed item.

To achieve this goal, a random number generator, containing a clock,

The 20 output of which is connected to the first input of the memory unit and to the counting input of the counter, the bit outputs of which are generator outputs, the second input of the counter is combined with

25 the input of the primary source of uniformly distributed random numbers and connected to the output of the comparator block, entered the adder, register (Memory and multiplier, first and second (the inputs of which are connected to

At the output of the primary source of uniformly distributed random numbers and to the first output of the memory block, the multiplier output is connected via a memory register to the first input of the comparison unit, the second input of which is connected via the adder to the second output of the memory block, the second input of which is connected to the output of the block compare.

The drawing shows the block diagram of the generator.

The generator contains 1 clock pulse generator, the first (source 2 evenly distributed random numbers, memory block 3, the first input of which is connected to generator 1 output, comparison block 4, the output of which is connected to the memory 3 inputs of source 2 and from the 5 , the other input of which is connected to the output of the generator 1. Source output

2 through multiplier 6 and memory register 7 is connected to the input of comparison unit 4, the other input of which through adder 8 is connected to output of the block

3 math tees, the other output of which is connected to the input of the multiplier 6.

Nowadays, statistical modeling methods are widely used to study the reliability of complex systems.

For this, probabilistic models of the systems under investigation are used. In most cases, these models can be divided into two main parts: structural, which is a formalized mapping of the system as a topological structure (graph), and algorithmic, i.e. a complex of algorithms that allow one to investigate the topological structure in order to obtain the necessary estimates, the realization of which can be carried out using appropriate devices.

The edges of the graph describing the system are the elements of the system and the vertices are the points of connection of these elements. Failure of some element of the system corresponds to the opening of the same edge of the graph.

In the simulation, the flow of system element failures is set, i.e. the flow of events consisting in the opening of the edges of the graph system describing and conducting a series of statistical tests of the graph for connectivity. At the end of the test, the scores are given. Lei system reliability.

“With this approach to solving the reliability problem, the most important element of the model is the failure flow generator: the accuracy of the final results depends on its quality.

In statistical modeling, the failure flow generator in each implementation must perform two main functions: generate moment

the time t at which the element failed in the system; indicate the number of the failed element, taking into account the probability of its failure, calculated at time t, i.e. determine where the failure occurred. The location of the failure is characterized by the number of this element in the system.

The algorithm of the generator is as follows:

1. For each i-th element of the system at time t, the probability of its failure Q (t) is calculated.

2. It is determined that J is equal to the sum of the probabilities of failures over all elements.

. (t),

one

where N is the number of elements in the system.

3. From the uniform distribution in the interval (0,1), the number g is selected, over which a random number is obtained.

gj-lj J.

evenly distributed in the interval.

4. For each successive summation, for the first sum, the condition f j Q -t (t) is checked; for each subsequent, ui (t)., S), where i sequentially takes the values 1,2, ..., k, ..., N.

For fixed gj, this inequality is satisfied only for some one value of k, which will determine the number of the failed element.

With a sufficiently large number of tests, the number of hits on the i-th segment of the interval O-f is proportional to its length (i.e. the value ((t)), which means that random events — element failures, characterized by drop-down numbers — are produced in accordance with probability distribution Q-, (t).

The generator works as follows.

In block 3, the memory records the calculated probability values for the failure of these elements ()

and their sum f. The generator is clocked by a clock pulse generator. The whole device is triggered by applying a pulse to the output circuit of the comparator unit 4. This starts the source 2 and resets the counter 5, and the first output of the memory unit receives the second input of the multiplier 6 value J. The clock pulses of the generator 1 are fed to the first input of the counter 5 for counting and to the first input of the memory block 3. With the arrival of each next (after starting the circuit) clock pulse, the SECOND output of memory block 3 at the input of the adder 8 receives the next one, starting with the first one.

the value (l (t) for summation. The first input of the comparison unit 4 through the memory register 7 from multiplier 6 receives a random number € y uniformly distributed in the interval (O, T). equal to the product of the value J from memory block 3 and v,. uniformly distributed in the interface (O, 1); source 2 coming from the output to the second input of the comparison unit 4 comes from the adder 8 accumulated sum-at-times the sum of the probabilities of element failures (t). As soon as the total 2jQv (t) exceeds the value of y, the comparison unit triggers an impulse for which from counter 5 the generator output receives a number equal to the number of clock pulses f3To calculated during the comparison time, the number corresponds to the minimum number)), calculated from the first, at which I4 is the sum Sj ((t) exceeded the value of §j, and, therefore, according to the algorithm, is equal to the number of the failed in the element system, the counter 5 is zeroed out, the memory unit 3 is brought to its outgoing state (i.e., to the address number). Next, the process of selecting the next failed element number for the next implementation is repeated.

Invention Form A random number generator containing a clock pulse generator.

the output of which is connected to the first input of the unit and to the counting input of the counter, the bit outputs of which are generator outputs, the second input of the counter is combined with the input of the primary source of uniformly distributed random numbers and connected to the output of the comparison unit, characterized in that generator capabilities due to

o forming a random stream of random numbers, it contains an adder, a memory register and a multiplier, the first and second inputs of which are connected respectively to the output of the primary

5 sources of uniformly distributed random numbers and to the first output of the memory block, the output of the multiplier through the memory register is connected to the first input of the comparison block, the second input

0 through which the adder is connected to the second output of the power unit, the second input of which is connected to the output of the comparison unit.

Information sources,

5 taken into account in the examination

I 1. USSR Author's Certificate 1 1855b9, cl. G About F 7/58, 1966.

2. USSR author's certificate, No. 260969, cl. G 06 F 7/58, 1968 (prototype).

Claims (1)

A random number generator containing a clock pulse generator, the output of which is connected to the first input of the memory unit and to the counter · input of the counter, the bit outputs of which are the generator outputs, the second input of the counter is combined with the input of the primary source of uniformly distributed random numbers and connected to the output of the comparison unit, characterized in that, in order to expand the functionality of the generator by generating a random stream of random numbers, it contains an adder, a memory register and a multiplier, the first and second inputs of which are connected respectively to the output of the primary source of uniformly distributed random numbers and to the first output of the memory block, the output of the multiplier through the memory register is connected to the first input of the comparison block, the second input of which is connected through the adder to the second output of the memory block, the second input of which is connected to the output of the comparison unit.