SU843216A1 - Analogue-digital converter - Google Patents

Description

(54) ANALOG-DIGITAL CONVERTER

I

The invention relates to electrical measuring equipment and can be used in information-measuring systems.

A known analog-to-digital converter of equilibrium, containing a threshold unit, a tat generator connected via a clock distributor to the input of the first digital-analog converter, and a series of matching elements connected in series, a trigger register and a second digital-analog converter CO

A disadvantage of the known analog-to-digital converter is low speed.

The analog-to-digital converter is known, which contains a set of threshold elements and an amplifier with variable coefficient, a trigger register and a voltage converter in the code comparison unit, a reference voltage sensor, a decoder and a key set:

However, the incorrect triggering of one of the threshold elements in the first conversion cycles causes an error that cannot be eliminated in subsequent cycles.

The purpose of the invention is to increase the accuracy of the conversion.

To achieve this goal, an analog-to-digital converter containing a clock oscillator, the output of which is connected to the input of a pulse distributor, at the same time coincident groups, a trigger register and the first digital-to-analog converter are connected, and the input inputs of the threshold elements are connected to the outputs of the voltage divider, the input bus is connected to the first input of the deduction unit, the second input of which is connected to the output of the first digital-to-analog converter, and the output to the second inputs of the threshold elements, the second digital-to-analog converter, zero-organ is introduced. the first, second, third, and fourth elements AND, the OR element, the first and second senators modulo two, the output of the subtractive unit being connected to the input of the zero-organ, the output of which is connected to the first input of the first element and to the first inputs of the first and second adders but module two, the outputs connected to the first inputs of the second and third elements AND, and the second inputs are connected respectively to the first output of the first threshold element and to the output of the OR element, the first input of which is connected to the output of the second threshold element and the second move - with the output of the fourth element And, the first input of which is connected to the output of the third threshold element, and the second input - with the second output of the first threshold element, while the second inputs of the first, second and third elements And connected to the output of the clock generator, and the output of the first element And it is connected to the first inputs of the first, fourth 3 i elements of the coincidence group, the second inputs of which are connected to the corresponding output of the clock distributor and to the corresponding trigger register, the output of the second The first element And is connected to the first inputs of the second, fifth 31 + 1 elements of the coincidence group, the second inputs of which are connected to the corresponding output of the clock distributor and the corresponding trigger of the trigger register, the output of the third element And connected to the first inputs of the third, sixth, 3i +2 elements of the coincidence group, the second inputs of which are connected to the corresponding output of the clock distributor TUX of pulses and the corresponding trigger of the trigger register, while the inputs of the second digital-to-analog converter a distributor connected to the outputs of clock pulses, and an output - to the input of the voltage divider the drawing shows circuit structures on the analog-to-digital converter. The proposed device contains a clock generator 1, the distributor n- (3i-2) times

1.-3/2 and „, and

2. -3/2 Uni

About 1

Oh oh

O O 64 clock pulses 2, D / A converter 3, group of elements of coincidence 4, trigger register 5, digital to analog converter 6, subtraction unit 7, null organ 8, first, second and third threshold elements 9, 10 and 11, voltage divider 12, first and the second adders 13 and 14 modulo two, the element OR 15, and the elements of the 1 & A / D converter work as follows. In each cycle of operation of the analog-digital converter, the determination of three binary bits of the output code occurs. In this case, the most senior of the defined bits is determined by the nullorgan 8, and for determining the other two, the threshold elements 9, 10 and 11, the voltage divider 12, the adders 13 and 14, the OR element 15 and the coincidence element 16 are used. voltage divider 12 to threshold elements 9, 10 and 11 are respectively supplied with voltage where where is the number of binary bits of the output code of the analog-to-digital converter; and, is the voltage corresponding to the younger discharge; i is the measure number. On the subtracting unit. 7s of the digital-to-analogue converter 6, the voltage U-, Y + n-Oi + 3 is applied, where 5 2 is the compensating -1 regulating voltage; r: 0, l - depending on the value of the j-ro bit. From the subtracting unit 7, the voltage is removed and Uy- U-, (where and is the transformed voltage), are fed to the nullorgan B and the threshold elements 9.10 and 11. At the same time, at the output of the zero-organ 8 there is 1 if U 0, and O, if and O, and O is present at the output of the threshold devices, if J exceeds the corresponding threshold voltage, and 1 at the inverse ratio. Depending on the U value, the following values are possible in n-t3i + 2) n- (31 + 1) n-3i-oM bits n- (3i-l) bit n-3i bit

3.-1/2

4. -l / 2 Utti

5.1 / 2 Ur,

6.Un. U

7.3 / 2 U, .Un-;

8..U 3 / 2Urv-; In all cases, the n- (3i-2) bit value corresponds to the logical concatenation at the output of the null organ; the n- (3i-l) and n-3i bit values represent the logical state at the output of the adder 13 and 14, respectively. With the arrival of the (i + l) -ro pulse, the values of certain bits are written through the matching elements (31-2), (31-1) and 3i of the group of 4 matching elements into the corresponding trigger register trigger 5. Similar. the algorithm of the analog-to-digital converter and in other cycles. Coincidence elements 17.18 and 19 serve to prevent false values from being written to the trigger register during a clock cycle, so that they are given a pulse at the beginning of the clock, the duration of which is shorter than the total response time of the group of coincidence elements 4, the trigger register 5 and the digital-analog converter 6 conversion accuracy is improved.

Claims (2)

  Analog-to-digital converter containing a clock generator whose output is connected to the input of a pulse distributor, a group of matching elements, a trigger register and a first digital-to-analog converter are connected in series, and the first inputs of threshold elements are connected to the outputs of a voltage divider, the input bus is connected to the first input of the subtracting unit, the second input of which is connected to the outputs of the first digital-to-analog converter, and the output to the second inputs of the threshold elements In order to improve accuracy, a second digital-to-analogue converter, a null-oro 1, is introduced. eleven about 1 Oh oh about i 1 1 gan, first, second, third and fourth elements AND, element OR, the left k second modulo two adders, the output of the subtracting unit connected to the zero-Morgan input, the output of which is connected to the first input of the first element And and to the first inputs of the first and the second modulo-two adders, the outputs connected to the first inputs of the second and third elements AND, and the second inputs are connected respectively to the first output of the first threshold element and to the output of the OR element, the first input of which is connected to the output of the second threshold element a, and the second input - with the output of the fourth element And, the first input of which is connected to the output of the third threshold element, and the second input - with the second output of the first threshold element j and the second inputs of the first second and third elements And connected to the output of the clock generator, and the output The first element And is connected to the first inputs of the first, fourth 31 elements of the group of coincidence, the second inputs of which are connected to the corresponding output of the clock distributor and the corresponding trigger of the trigger register, the output of the second element I is connected to the first inputs of the second, additional 3i + l elements of the coincidence group, the second inputs of which are connected to the corresponding output of the clock distributor and the corresponding trigger of the trigger register, the output of the third element I. connected to the first inputs of the third, sixth 3i + 2 elements of the coincidence group, the second inputs of which are connected to the corresponding output of the clock distributor and the corresponding trigger register, while the inputs of the second digital-to-analog converter are connected to the outputs of the clock distributor, and the output to the voltage divider . Sources of information taken into account in the examination 1. USSR author's certificate 330538, cl. H 03 K 13 / 17.08.06.70 843216 2. Shl ndin: V.M. Digital measuring transducers and devices. M., Higher School, 1973, pp. 239-240, fig.4.29.