SU842868A1 - Analogue-digital integrator - Google Patents

Description

(54) ANALOG-DIGITAL INTEGRATOR

I

The invention relates to computing and can be used to accurately integrate both rapidly changing and slowly changing values.

There are analog-digital integrators that combine high accuracy with the ability to integrate functions of both rapidly changing and slowly changing, containing converters of digital information into analog, analog integrator and adder 1 and 2.

The closest in technical essence to the proposed is an analog-digital integrator containing a digital-to-analog converter (DAC) in the input circuit, an analog integrator (AI) connected in series with it, two comparators K1 and K2 connected by their first inputs to the output of the IA, the outputs of the comparators are connected the inputs of the counter-adder (MF-CM), the output of which is the output of the entire device. The second input of the comparator K1 is supplied with the comparison voltage Uef, and the second input of the comparator K2 is the voltage Ue obtained using the inverter In. For zeroing

the integrator of the AI when any of the comparators are triggered is the adder Cm, the inputs of which are connected to the outputs of the comparators K1 and K2, and the output to the control input of the integrator 3

In the initial state, the input of the DAC is filled with zeros in all bits. The integration accuracy, in addition to other factors, is influenced by the difference from the calculated values and the temporal and temperature instability of the parameters of the analog part of the circuit: the constant time of the analog integrator, the values of the voltages Ucp and Don- If we accept that Ucr and Uon are highly stable and equal to the calculated, then the error in the integration due to the reasons given is equal to

-iV

OK „tl-l / -1

15

 Ucp-TT

relative error is determined by

20

This error is at least half the total integration error and is not compensated, while the other components of the total integration error can be at least partially compensated. The accuracy of such an integrator is low and amounts to a few tenths of a percent, which makes it impossible to use multi-bit (more than a network — eight bits) codes in it. The purpose of the invention is to improve the accuracy of integration of the analog-digital integrator. The goal is achieved by the analog-to-digital integrator containing serially connected digital-analog converter, the input of which is connected to the input of the analog-digital integrator, analogue integrator, comparator and inverter, the output of which is connected to the first input of the adder, the second input of the comparator is connected to a zero potential , and a summing counter, an integral increment sign determination block, two keys, a counter, an additional inverter and a multiplier, whose inputs are connected to the output, are entered. am counter and comparator, and the output to the control inputs of the digital-to-analog converter and the first key connected between the clock pulse and the first input of the summing counter, the second input of which is connected to the analog integrator output and the output to the digital-analog output the integrator, the second switch is connected between the clock pulse bus and the counter input, the output of which is connected via an additional inverter to the second input of the adder, the output of which is connected to ravl yuschemu second key entry. The drawing shows the scheme of the proposed device (an example of a specific embodiment). The analog-to-digital integrator contains a DAC 1 with the input circuit, the output of which is connected to the input of the analog integrator 2, and the output of the integrator 2 to the first input of the comparator 3 and the input of the unit 4 for determining the sign of the integral increments. The output of block 4 is connected to the control input of summing counter 5, the output of summing counter 5 is the output of the entire device, and the input is connected via the first key 6 with a clock width. The output of comparator 3 is connected to the first input of multiplication unit 7 and to the input of inverter 8. The second input of multiplication unit 7 is connected to the input of additional inverter 9 and output of counter 10, and the output with control inputs of the first key 6 and digital-analogue converter 1. Inverter outputs 8 and the inverter 9 is connected to the inputs of the adder 11, and the output of the adder 11 is connected to the control input of the second key 12. The input of the second key 12 is connected to the clock pulse bus, and the output is connected to the input of the counter 10. In the initial state, the voltage at the output of the analogue integral ora 2 is zero, the inputs of the DAC 1 filed zeros in all bit input code rows and the voltage at its output is also zero. The signal at the output of the comparator 3 is zero, the summing counter 5 and the counter 10 are zero, therefore the signal at the output of the multiplication unit 7 “O, which corresponds to the“ Integration ”cycle, the first key b locked and the digital-to-analog converter 1 converts the input code x into the output signal . At the outputs of the inverter 8 and the inverter 9 - the signal “1”, at the output of the adder 11 - also the signal “1, as a result of which the second clue 12 is open. The output state of the determinant of 4 digits of the integral increments on this is indifferent. At the initial time, a non-zero code and a sequence of clock pulses from the generator are simultaneously applied to the input of the DAC 1 and to the clock pulse band. In this case, a voltage appears at the output of the D / A converter, which is defined by the following expression -JJPn-K.-JC where and is the voltage of the internal reference voltage source of the D / A converter 1; JC is the current value of the input code; . maximum value of the input code; K, is the transfer ratio of the DAC 1 at X X m. We introduce the designation The voltage at the output of the analog integrator 2 varies according to the following law 11, -1 fU; dt is: ll7, t, is the time constant of the analog integrator 2. When the output voltage integrator 2 exceeds the threshold of the comparator 3, the output of the comparator 3 is the signal "1, the signal at the output of the inverter 8 is zero. Counter 10 through the open second key 12 is filled with clock pulses, followed by a period T. When counter 10 is full, the signal "1." Appears at its output. and the output of the inverter 9 signal- "0. Thus, on both inputs of the adder 11 are zeros, the state of its output is also zero. The second key 12 is locked. Both units of the multiplication unit 7 are fed with "units" from the output of the comparator 3 and from the output of the counter 10, the output of which also shows the signal "1, which opens the first key 6 and switches the DAC 1 to the state when life corresponding to x ... IT / f No. Q is IT, -cfx,. The sign and, opposite to U, on the integration cycle. The integration cycle is completed, the second cycle started - reading. By the time the reading starts, the voltage at the output of integrator 2 is J2a. - 4 and. t ". where ty is the integration time. Taking into account that, and the integration time is determined by the expression (), (2) where m is the counter size 10, we rewrite (1) as a game. (2 -1) During the read cycle, the voltage at the output of the integrator 2 varies law, u- -u - "- 47b; c (t)) And at a certain point in time becomes equal to zero. At this moment, the signal at the output of the comparator 3 is changed to "O", which, through the multiplication unit 7, locks the first key b and switches the digital-to-analog converter 1 to a state where the voltage at its output is determined by the current value of the input code X. the signal through the inverter 8 and the adder 11 causes the second key 12 to be unlocked, through which the clock pulses arrive at the input of the counter 10. This completes the read cycle and begins the second integration cycle. The duration of the read cycle is determined from the expression (3) at Uj О t ,,. I: nK: () ЗСмАКС During the integration cycle through the open first key b, the clock pulses go to the input of the summing counter 5, which fill it. They arrive at t, t ,, This number is equal to the increment of the integral M AY Taking into account (4 (we get the expression, y.) (5) tnaice) As a result of summing the increments AY defined by expression (5), we get the full value of the integral over time t Nt. As is well known, the approximate value of the integral of a function is defined as follows: V-IWii Y .SXiAU AU2: xi., Iz.0 where theXX is the value of the integrand at the beginning or end of the segment AU; A and is the increment of the argument: that A and const are all the integration interval. It is also assumed that the initial value of the integral Y is zero. e x1L U is the increment of the integral of the function x on the i-th integration interval. AYi XiAU In the proposed device, the value of the integrand function xi at the beginning of each integration interval is given as a binary code x to the input of the digital-analog integrator. arriving at the input of summing counter 5, which in fact is a value equal to the integral increment, depends only on the current value of the input code X and does not depend on the accuracy and stability of the parameters of the elements included in Technical contents are subject DAC 1 and 2. The equivalent analog integrator time constant T of the digital-analog integrator is of the expression (5), provided x Y (x const) T, cit Y x, 1. but aT () G, thus, Te Te Tx For the time of the analog-digital integrator also does not depend on the parameters of the elements of the analog part of the device. In the counter-adder 5 accumulates the number of rDF, WH Y.IX, --O. When comparing (6) and (7), it is seen that the number (1) / x is the increment of the argument of the integrand function L II - - au - From the expression (7) it follows that the accuracy of the integration is not affected by the values of any parameters of the analog part of the circuit, and consequently, their temporal and temperature changes. As can be seen from the foregoing, in the proposed device, this component of the error is missing, which causes the integration accuracy to be at least twice as high as in the known device.

Claims (3)

1. USSR author's certificate number 556463, cl. G 06 J 1/00, 1975. 2. The patent of France No. 2367319, cl. G 06 G 7/18, published 1978 3.Galperin M.V. Accuracy, reliability, speed. M., “Science, 1976, p. 138, 159 (prototype).