SU841008A1 - Information receiving device - Google Patents

Description

(54) DEVICE FOR RECEPTION OF INFORMATION

one

The invention relates to a technique for receiving information and can be used in apparatus for receiving information from interference channels.

Devices for decoding the code-pulse parcel of the start of a telecode information reception (marker) cycle are known, containing a clock generator, an information reception shift register and a matching circuit.

However, known devices do not allow decoding a marker with a permissible distortion in t-bits. The number m characterizes the noise immunity of the marker-type code sequence and is calculated using the theory of cyclic codes.

The closest in technical essence to the present invention is a device for receiving information, containing an input register, whose information input is connected to the device input, a clock pulse generator, the output of which is connected to the clock inputs of the input register and a comparison element, which is connected to the output of device 2.

The disadvantage of the known device is the impossibility of decoding code.

parcels of the marker type with a permissible distortion in m bits, which reduces the noise immunity of receiving information.

The purpose of the invention is to improve the noise immunity of receiving information.

The goal is achieved by introducing a shift register, a counter and a clock frequency multiplier into the device, the inputs of the input register are connected to the corresponding first inputs of the shift register, the clock pulse generator is connected to the second shift register inputs via the clock multiplier,

5 whose output through the counter is connected to the input of the reference element.

The drawing shows a diagram of the device.

The device contains an input register 0 register 1, a shift register 2, a counter 3, a reference element 4, a clock generator 5 and a clock frequency multiplier 6.

The device works as follows.

5 way.

The code-pulse information enters the n-bit input register 1 for receiving information, the number of bits is equal to the number of symbols in

Claims (2)

0 sprinkle (marker) start the cycle. The bit outputs of the information receive register are connected to the bit inputs of the n-bit shift register 2 in such a way that, if an undistorted marker is located in the information receive register completely in a certain time tick, the units and zeroes of the marker are written (i.e., a bitwise comparison of the bit of the undistorted marker, expressed by the number of units written to shift register 2, is performed for each tick of receiving the code-pulse information) The value of the number of ones in register 2 of the shift tyvaets in counter 3 with a clock frequency of at least f {n + 1) supplied from the multiplier 6 with the clock, the input of which L 5 is the generator output clock frequency, where f - frequency clock pulses, ti - number of marker symbols. The selection of the pulse of the beginning of the reception cycle of information occurs at the output of bitwise comparison element 4 whose inputs are the corresponding outputs of the counter bits. The coincidence circuit extracts a number (p - t), where m is the maximum allowable number of distorted characters in the marker, which is determined by the noise-resistant properties of the latest. What was the last bit of the marker taken? Thus, the proposed decoder, in connection with the use of the distorted shift register symbols, the counter and the clock frequency multiplier, as an analyzer, provides a distorted marker in t-bits. An apparatus for receiving information, comprising an input register, an information input of which is connected to an input of a device, a clock generator, the output of which is CONNECTED to the clock inputs of an input register and a comparison element whose output is connected to an output of a device to increase noise immunity, a shift register, a counter and a clock frequency multiplier are entered into the device, the bitwise parallel outputs of the input register are connected to the corresponding bit pair To the direct inputs of the shift register, the output of the clock generator is connected to the clock inputs of the shift register through a multiplier of the clock frequency, the output of which is connected to the input of the comparison element through a counter. Sources of information taken into account in the examination 1. Drozdov E. A. and P. Tibratov A.P. Automatic conversion and encoding of information. M., Sov.radio, 1964, p.432 and 459. 2. USSR author's certificate number 267184, cl. G About F 3/00, 1962 (prototype). f u r a Р 2Р h. . .