SU813431A2 - Logic unit testing device - Google Patents

Description

one

The invention relates to computing and can be used to control logical nodes.

According to the main author. St. No. 469971 knows a device for controlling logical nodes, containing an address switch, the first output of which is connected to the first input of the malfunction analysis and logic processing unit, a random access memory unit, the first and second outputs of which are connected to the control unit, the third output to the first input of the generating unit stimulus, and the fourth to the fault analysis and logic processing unit, the outputs of the control unit are connected to the second and third inputs of the stimulus unit, three outputs of which connected to the switching unit of stimulating effects, and one output to the troubleshooting unit, the outputs of which are connected to the second input of the malfunction analysis and logic processing unit and the first input of the operating memory, in addition, the device additionally contains a fault memory unit connected by the input with the fault detection unit, and the output with the third input of the logic analysis jd fault analysis block, one output of which is connected to the control unit and four outputs to the address comm tator, the second output of which is connected to the memory block {.

A disadvantage of this device is its low speed, since it is limited by the time required to form a code pattern of a stimulating effect when testing any logical block.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that a clock pulse generator and a counter are entered into the device for controlling the logical nodes, the counter output is connected to the corresponding fault detection input, the first counter input is the device input, the second input

the counter is connected to the output of the clock generator, the signal input of which is connected to the fourth output of the fault analysis unit and the reception of the clock pulse start input is connected to the sixth output of the RAM. The drawing shows a block diagram of the device. The device contains a block of 1 memory, a generator of 2 clock pulses, a control block 3, a counter 4, a stimulus generation block 5, a stimulus switching block 6, a device input 7, a fault detection block 8, a fault memory block 9, a block 10 analysis of faults and solves, register 11. routines, fault register 12, cycle register 13, return register 14, address switch 15. . The main memory unit 1 serves for snooping control programs and is a memory device with random access to the memory cells at the address specified by the address switch 15. The generator 2 clock pulses at the command of the RAM 1 generates clock pulses with the necessary frequency of checking the counters installed on the checked blocks. The control unit 3 serves to arrange the stimulator generator bits in accordance with the RAM command and determines the interaction of the stimulus generator bits. A counter 4, which is preliminarily inputted to entry 7, records an additional code of the number of clock pulses necessary for supplying to the logical node being checked, counts clock pulses. The stimulation generation unit 5 forms code combinations of the required length, generates a series of combinations according to the law established by the control unit, serves to establish the amplitude-temporal characteristics of the stimulating effects. The stimulation switching unit 6 sends a sequence of code combinations to the pr-object. The troubleshooting unit is designed to determine whether a test object is faulty and to determine compliance with the test object's reaction program. The fault memory block 9 serves to accumulate the results of the individual monitoring steps. Fault analysis and decision block 10 determines the nature of the fault and switches the device to its localization. The registers of subroutines 11, failures 12, cycles 13, returns 14 serve for storing and issuing addresses of block 1 of RAM, which need to be addressed in accordance with the resolution adopted by block 10 for analyzing faults and making decisions. The device works as follows. The stimulating actions generation unit 5 upon a command from the RAM unit 1 generates a series of code combinations, which, through the switching unit 6, sends the stimulating effects on the test object. Code combinations, the test object's reactions are accumulated in the fault detection unit 8, in which, after the end of the work of the stimulus generator, the packet information is compared with the reference one. When the accumulated and the reference memory information coincides, a command is issued to the stimulus generator to send the next code combination to the test object, etc. If a counter is installed on the test object, then the command of the main memory unit 1 checks the combination part first Then, using the stimulating effects generation unit 5, through the stimulation switching unit 6, the stimulation code is set at the inputs of the combination part. effect, a remaining unchanged upon further inspection. Then, through the device input 7, an additional code of the number of pulses required for supplying the counting inputs of the test object is recorded in the clock counting unit. The main memory unit 1 starts the generator of 2 clock and commercial pulses, which sends pulses with the required frequency through the switching unit 6 of stimulating effects on the test object and simultaneously to the input of the counter 4. If the output pulse of the counter coincides with the pulse of the test object’s response In block 8 for troubleshooting, block 10 for analyzing faults and making decisions stops the generator of 2 clock pulses. To establish the area of stable operation of the test object, the fault analysis and decision analysis unit 10 issues a command to the control unit 3 to repeatedly search through code combinations by the stimulating generation unit 5, for the counting test objects, it includes a generator of 2 clocks, at the address written in the 13 cycles register, calls the subroutine for checking the area of stable operation of the object being checked. If the accumulated and reference information does not match, the fault analysis and resolution module 10 generates a command for accessing the fault localization subroutine via register 12. The subroutine address is written by memory unit 1 to register 11 subroutines. Block. 1 in this case, through the block 5 of the generation of stimulating influences and the block 6 of the switching of stimulating influences, the system provides code combinations to the test object. All cases of inconsistencies between the reactions of the test object and the standard are recorded by the block 9 of the fault memory. At the end of the subroutine, the fault analysis and decision making unit 10 determines the type of malfunction and proceeds to the next program section at the address recorded earlier in the return register 14 from the address switch 15 at the moment of the transition to the malfunction localization subroutine. In the absence of malfunctions at the end of the entire control program, the inspection object is considered to be intact.

Claims (1)

1. USSR author's certificate No. 469971, cl. G 06 F 13.12.73 (prototype).