SU813365A1 - Interpolator - Google Patents

Description

one

The invention relates to automation and computing and can be used in various nporpaNMHoro control systems that have code outputs.

The interpolator is known; it is built on two negative feedback, digital differential angles, each of which consists of series-connected accumulator of block block, transfer key and integrate register (or counter), and overflow output the accumulating adder of one integrator is connected to the input of the counter of the integrand of the second and vice versa, with one of these connections being connected to the summing input of the counter and the other to the subtracting flj. The disadvantage of this interpolator is the difficulty of programming the digital sine of the frequency and the low accuracy of obtaining the digital sine of the specified different frequencies. Closest to the invention is an interpolator containing AND and OR elements, serially connected first reversible, first key block and first accumulating adder, sequentially connected first suction counter, first pulse shaper and first AND element, successively connected second reversible counter, second block keys and a second accumulator, an adder, as well as a second summing counter, connected in series, a second time pulse and a second And element, the outputs of the first second pulse shapers connected to the corresponding third AND vhodsSh and pulse generator output - to the input of the fourth AND gate 2.

five

The disadvantage of such an interpolator is that it is not suitable for reproducing the dependence R cosF and R sln-Ps volume, if it is necessary to provide a predetermined frequency of change of the siPH and eovF function, but not a given speed of movement of the point with coordinates XR cos4 and y - R sin around the rshius radius R. Number;

5 argument pulses when changing the magnitude of the radius (amplitude) R is necessary for interpolating the total period of the sinusoid in the interpolators built on the basis of digital differential analyzers (CDL),

0

is not constant and varies depending on the amplitude and in interpolators built on the basis of the evaluation function, there is no connection at all between the coordinate displacements and the argument, since it works in the CapiroBHX coordinates using the formula L y, i.e. builds the dependencies y - f (x). Thus, this interpolator does not allow simple and accurate generation of digital sine codes of given frequencies.

The purpose of the invention is to expand the functionality of the interpolator.

. The goal is achieved by adding an adder, the first trigger and a frequency divider, the second trigger and the second frequency divider serially connected to the interpolator, the third summing counter, the decoder, the encoder, the third key block, the third accumulating adder and the third trigger, and also connected fourth summing counter, fourth block of keys, fourth accumulating adder and third frequency divider, the output of which is connected to the first inputs of the fifth and sixth elements AND, connect the second inputs OR through the first and second elements OR to the corresponding outputs of the decoder, the first input of the third element OR is connected to the output of the sixth element AND, the second input through the first frequency divider with the output of the fifth element AND, and the output through the series-connected seventh element AND, the fourth element OR, the eighth “my element AND” and the ninth element “AND” with the input of the fourth summing counter, the input of the first tripper under is connected to the output of the third element AND, and the output through the eighth element AND to the second inputs of the first and second And elements connected to the second inputs of the first and second key blocks respectively, the output of the fourth element I connected to the input of the second trigger, the second input of the third trigger connected to the output of the second frequency divider, and the output to the first input of the ten And element whose output is connected with the second of the third and fourth ktchik blocks, and the second input - with the second output of the second trigger and with the first input of the eleventh AND element connected by the second input to the second input of the ninth AND element and to the input interpol torus, and output - to the second input of the fourth OR gate, the adder input connected to the inputs of the first adder and second counters and reversing yield the first accumulator and the output of the second accumulator to the inputs of the first and second summing reverse counters.

Figure 1 shows the structural scheme of the interpolator; Fig. 2 illustrates a digital sinusoid with accepted symbols.

Interpolator (FIG. 1) “enters the first 1 and second 2 reversible counters, the first 3 and second 4 blocks of keys, the first 5 and second b accumulating adders, the first 7 and second 8 summing counters, the first 9 and second 10 pulse shapers, the first 11 , second 12 and third 13 element AND first trigger 14, eighth 15 and ninth 16 elements AND, fourth element OR 17, block 18 disk selection, reversible counter 19, pulse generator 20, fourth element AND 21 second trigger 22 and frequency divider 23 , the tenth 24th and eleventh 25 elements And, the third trigger 26 w. summing counter 27, decoder 28, encoder 29, third key block 30 and accumulating adder 31, fourth summing counter 32, key block 33 and accumulating adder 34, third frequency divider 35, fifth element AND 36, first frequency divider 37, third element OR 38, the seventh element And 39, the second element OR 40, the sixth element And 41, the first eoment OR 42 and the adder 43.

The interpolator operates in two modes: in auxiliary mode (CalculationF) and in the main mode of generating the digital sine of a given frequency and amplitude (Operation).

Claims (2)

Auxiliary mode Calculation is used to calculate the value of the argument Ф, corresponding to a quarter of a digital sine wave of a given amplitude. Before starting work in this mode, the information is distributed according to the device: in sukylators 5 and 6 the machine unit is entered, i.e. 100000, counters 7 and 8 are the code of the amplitude of a sinusoid A, code 2 of the code of the sinusoid A is entered into the counter 2, and counter 1 is set to the zero state, the potential, the opening elements AND 16 and 25 are entered into the interpolator, after which the signal is received The start-up, the installation of the trigger 14 into one state, the element And 21 is opened, the element 39 is closed, because the potential Work in this mode is absent. The frequency f p of the oscillator generator 20 through the element And 21 enters: at the counting input of the trigger 22, where it is divided into two frequencies f and fij. shifted relative to each other by 18C. The frequency ff through the element And 25, the element OR 17 and the element And 15 (opened by a single output signal of the trigger 26) is fed to the inputs of the elements And 11 and 12, as well as the outputs on the control inputs of blocks 3 and 4, which adds to the numbers stored in the adders 5 and 6, codes from counters 1 and 2. The overflow signal of adder 5 subtracts one from counters 2 and 7, and the overflow signal; adder 6 subtracts one from counter 8 and adds it to counter 1. This corrects the values of the integrand functions and increments for both coordinates. The overflow pulses of the adder 5 in this mode are increments of the cosine, and the overflow pulses of the adder 6 are increments of the sine. This will continue as long as counters 7 and 8 are not adjacent in the zero state. Then, drivers 9 and 10 prohibit the passage of argument pulses through elements 11 and 12, respectively, and as soon as both counters 7 and 8 are in zero position. The element And 13 triggers, and with its output signal it sets the trigger 14 to the zero state, the element 15 closes, and a quarter of the digital sinusoid period is completed. The number of pulses of the argument that has passed during this time through the element 15 is received through the element 16 and the potential-open calculation at the input of the counter 32, where it is counted. The mode task is completed, the value of the number for a given amplitude is determined. The computation time is minimal, since the interpolator operates at high frequency f, and not at the output frequency of the output sine frequency setting unit f. After the completion of the calculation mode, the interpolator automatically switches to operating mode, i.e. generating a digital sine of a given amplitude and frequency. Before starting work in the operating mode, the information is distributed into the device blocks as follows: machine units in actor 5 and 6, digital sine amplitude A in counters 1, 7 and 8, average value of digital sine A in counter 19, the value of the argument corresponding to the amplitudes A, in the counter 32, the number of the frequency Nf corresponding to a certain frequency of the digital sine F, in the counter 27. Potential Calculation is absent, and the Potential is present in the circuit. The Start signal sets the trigger 14 to one and open1% ha element is 21. And the frequency pulses go on element 24. And element 25 is closed. The pulses of the frequency f BOCTyna are fed to the input of the divider 23, from the output of which each nth pulse arrives at the single input of the trigger 26 and sets it to the single state. In this case, the element 24 opens, and the frequency pulses f from its output arrive at the direction of the inputs 30 and 33, and the codes from the output of the encoder 29 and counter 32 are added to the codes in adders 31 and 34, respectively. The overflow pulses of the adder 34 through divider 35, element AND 36 or 41, therefore, through divider 37 and element OR 38, through element AND 39 opened by the Work signal, and further through element OR 17 arrive at the input of elements AND 11 and 12, which transmit these signals for the same test as in Run mode only at a significantly lower clock frequency. The difference is that in this mode the block 17 is open and transmits the overflow pulses of the adder 5, i.e. increments of the sine to the inputs of the counter 19, as a result of which in this counter 19 the combination of codes changes according to the law depicted in FIG. The overflow pulses of the adder 31 set the trigger 26 to the zero state, and therefore the frequency of the overflow pulses of the adder 31 is exactly equal to the frequency at the output of the divider 23. The code supplied to the input of the block 33 is generated as follows. The frequency number of the digital sine wave is recorded in counter 27, decrypted by decoder 28 and encoded into some auxiliary number by encoder 29. Elements OR 40 and 42 combine the numbers of frequencies that require or do not require the inclusion of divider 37, i.e. provide automatic selection of the digital sine generation range by including the keys of the And 36 and 41 elements. The auxiliary number value is determined as follows. It is necessary to generate a digital sine frequency of 25 Hz, then the period is 0.04 s, and a quarter of the period, respectively, 0.01 s. All dividers have division factors of 10, and generator 20 has a frequency of 5 MHz, then f fa, 2.5 MHz. The frequency at the output of the divider is 23-250 kHz, the frequency at the output of the overflow of the adder 31 is also 250 kHz. We determine the number of pulses of frequency 250 kHz, which will pass in time T / 4, i.e. for 0.01 s N 2500, encode in the block as an additional 250 and turn on one divider 35 by 10, for which we open the element AND 41. Then, until the output of the overflow of the adder 31 takes 2500 pulses, which will occur during T / 4 (0.01 s), for interpolation will arrive smooth pulses, i.e. the number of pulses equal to the argument or exactly necessary for the interpolation of a quarter sine wave. When the amplitude A of a given sinusoid changes in the Calculation mode, the new value of the argument value will be calculated, and as a result, the frequency of the digital sinusoid will remain unchanged, i.e. AJ A,., J, as F ,, (figure 2).,. Thus, the interpolator provides automatic maintenance of the preset frequency when the digital sine tone changes, which is not generally achieved in known interpolators or requires recalculation of the frequency fj, which is inconvenient since it is practically impossible to calculate the frequency j precisely. As a result, sinusoids are generated not only different in amplitude, but also in frequency from each other in frequency by an unrecorded value, i.e. The problem is not precisely solved, but with a large error, which is unacceptable when controlling specific objects and is especially harmful when used. In the case of an interpolator in the composition of measurement boards OV, since this can lead to absolutely incorrect results. The proposed interpolator provides for the generation of the digital sine of any amplitudes with an accuracy in amplitude within one discrete interval and a period accuracy within the stability of the master oscillator, i.e. values of order 10. Formula of Invention Interpolator containing AND and OR elements, serially connected first reversible counter, first key block and first accumulating adder, sequentially connected first summing counter, first And-shaper generator and first AND element, successively connected second reversible counter , the second block of keys and the second accumulating adder, as well as successively connected second summing counter of the second form: pulse generator and the second element I, outputs of the first and Some pulse shapers are connected to the corresponding inputs of the third element I, and the generator of pulses is connected to the input of the fourth element I, from l and ch and so that, in order to extend the functionality of the interpolator, in neg entered the adder, the first trigger and the frequency divider, the second trigger and the second frequency divider connected in series, the third summing counter, the decoder, the encoder, the third key block, the third accumulating adder and the third trigger, and the follower The fourth summing counter, the fourth key block, the fourth accumulating adder and the third frequency divider, the output of which is connected to the first inputs of the fifth and sixth AND elements, connected by second inputs through the first and second elements OR to the corresponding outputs of the decoder4, the first input of the third element OR are connected with the output of the sixth element And, the second input - through the first frequency divider with the output of the fifth element And, and the output through the series connected in series. the seventh Element And, the fourth element OR, the eighth The second element And the ninth element And with the input of the fourth digital counter meter, the input of the first trigger under; connected to the output of the third element And, and the output through the eighth element And to the second inputs of the first and second elements And connected by outputs to the second inputs of the first and The second key block, respectively, the output of the fourth element And is connected to the input of the second trigger, the second input of the third trigger is connected to the output of the second frequency divider, and the output to the first input of the ten element And, the output of which is connected to the second inputs of the third O and the fourth key block, and the second input — with the second output of the second I trigger; with the first input of the eleventh AND element, connected by the second input to the second input of the ninth AND element and to the interpolator input, and the output to the second input of the fourth OR element, the adder input is connected to the inputs of the first summing and second reversing meters and with the output of the First accumulating adder, and the output of the second accumulating adder with the inputs of the first reversing and second summing accounts. Sources of information taken into account in the examination 1. V. Kisilev. Phase systems. numerical software equation. I., Mechanical Engineering, 1976, p. 133336. 2. Authors certificate of the USSR 555381, class G 05 B 19/18, 1975 (prototype).