SU809575A1 - Analogue-digital device for comparing rated signals - Google Patents

Description

(54) ANALOG-DIGITAL DEVICE FOR COMPARING NORMALIZED SIGNALS

I

The invention relates to a pulse technique and can be used in systems for automated measurement of radio interference, monitoring operator performance, technical diagnostics, monitoring the noise immunity of information transmission lines, etc.

Analog-digital devices for q aBHeHHH of normalized signals are known, which contain perceptual and storage units of measured values, storage units of exemplary standards, logical units that compare reference and measured values 1 and 2.

The disadvantage of such devices is their limited functionality, which allows them to be used only for compared measured and exemplary values, which limits the scope of use only by control systems.

The closest in technical essence to the present invention is an analog-to-digital device for comparing normalized signals, comprising an analog-to-digital converter and a display and recording unit 3.

A disadvantage of the known device is its limited functionality, which allows it to be used only for assessing whether the measured value is within a predetermined tolerance, which allows its use in automatic control systems.

The purpose of the invention is to extend the functionality of the device.

Claims (2)

This goal is achieved in that an analog-to-digital device for comparing normalized signals containing an analog-to-digital converter and a pickup and recording unit is inserted into a memory block, logical elements Equivalence OR "master oscillator, second, third, decoder, second and third logical blocks, time comparator {Shtarvalov, with the first and second inputs of the front-end memory block connected to the corresponding outputs of the analog-digital converter into the inputs of the logic element Equivalent g, the output of which is connected to the first one at the first logical unit and, through a series 38 connected one-shot and logical element OR, to the third input of the edge memory block whose outputs are connected to the corresponding inputs of the decoder, the first and second outputs of which are connected to the corresponding inputs of the second logic block, the third input of which is connected to the second input of the first logic block, the first input of the time interval comparator and the output of the master pulse generator, and the first and second outputs from the third output is connected to the third input of the first logic block, the first and second outputs of which are connected to the corresponding input of the local indication and registration, the fourth output of the second logic block is connected to the second, input of the logic element OR, the third and the fourth outputs of the decoder with the corresponding inputs of the third logic block, the first and second outputs of which are connected to the corresponding inputs of the display and recording unit, and the third output to the second input of the computer Ator time of intervals whose output is connected to a fourth WMOs house the first logic block. FIG. Is a block diagram of the device; figure 2 is a temporary diagram of his work. The proposed device (FIG. 1) contains an analog-to-digital converter 1. a front memory block 2, logical equivalence elements and OR 3 and 5, - one-shot 4, a decoder 6, first, second and third blocks 7, 8 and 9 of logic, 10 pulse generator, comparator 11 time intervals, indication and registration block 12. The device compares two signals - real and software (D and Pr) converted to the normalized view (a sequence of pulses of the same amplitude), see Fig. 2, graphs U, L. The information carried by the signals is displayed in the form of pulse duration and their location time axis. As a result of the comparison of signals, the device produces the following estimates: for a certain time interval, there is a psr or a missed impulse of a valid signal q asHeH ffi) with software, the display is performed by jgeneihibiMH signals Licekie Skip, respectively, U charts, UJp Fig.2; There is a lag or advance in transmitting and falling fronts of the signal L OTHO, the indication is made by relay loops Late and Tano, respectively, tr & and Up 2, exceeded when specified beyond the tolerances (indicated by arrows in the figure OCP figure 2), and also fixing the absolute value of the latency or advance time, the graphs Un and Up of Fig. 2. (In Fig. 2, the numbers 1JI, P, IV denote possible correlation of signals -p and MA for explaining the operation of the device. Option I displays the early start and late termination of the sensor signal relative to the program, thus forming signals whose duration corresponds to the lag time, advance (Up, Un graphs) and Relay Early Late signals (Up, Un graphs. Option P displays the coincidence of the JA and Unp signals within the specified tolerance field, at the same time, only the advance or lag time of the graphs (% Un charts) are formed. Option 1 and displays the pulse bypass of the sensor relative to the program, and the relay signal is skipped (the Unp graph). beginning of the signal from the sensor on the program and the occurrence of extra pulses from the sensor with respect to the program, the formed signals described graphs Up, Un, Un, Unp, yl- apparatus operates as follows. Signals real (D) and software (Pr) from the sensor are converted to a pulse (normal) form in block 1, from the output of which they go to block 2, in which the front and back edges of the D and Pr signals in the input voltage levels are memorized at the exits. At the same time, the normalized signals D and Pr come to logic element 3, the output of which, when they are identical, generates signal 1, which triggers the one-shot 4 and, through logic element 5, provides a reset of the storage elements of unit 2, whose output signals are at. this is filmed. If the signals D and Pr do not match at the output. element 3, a signal O is formed, in block 4 the formation is not performed and the reset signal is not received in block 2. Unit 2, depending on the situation (for example, variants I, ti, W, PG of Fig. 2 and GP) generates a corresponding code arriving at the inputs of the Leshifrator b, which at its first and second outputs generates signals of the Highest, Missing Impact. These signals are sent to the corresponding inputs of block 8, which produces their formation over time and transfer to block 12. Block 8 simultaneously generates signals on the third and fourth outputs, which provide a reset in block 2 (through logic terminal 5) and in block 7 on signal generation time is Extra, Missing (graphs and DSC of FIG. 2). At the third or fourth outputs of the decoder 6, if there is a corresponding situation, the lag or advance signals are generated, respectively, the duration of which is proportional to the lag (advance). These signals are sent to block 9, where they are formed and transmitted to block 12 (graph Up, (J fit 2.) to indicate delay times or advances along signal fronts. At the same time, the third output of block 9 and block 11 receives a signal proportional to the delay or advance on the fronts. In block 11, depending on the selected setpoint, the relay signal is set, formed, and the signal goes beyond the tolerance field. This signal goes to block 7. Block 7 performs the formation of time signals Early and their transfer to block 12 (Unl Up graphs of figure 2), as well as blocking the issuance of these signals depending on the presence of a signal. The resolution coming from the output of block 3. The time signals in blocks 7, 8 and 11 are produced using a gauge. time generator pulses 10. Formula of the invention Analog-digital device for comparing normalized signals, containing an analog-to-digital converter and a display and recording unit, characterized in that in order to expand the functionality of the device, front-end memory block, Equivalence logic elements, and OR, pulse generator, one-shot, decoder, first second and third logic blocks, time interval comparator, when 5g the first and second edges of the front-end memory block are connected to the corresponding outputs of the analog-digital converter and inputs of the Pa-nospachy logic element, the output of which is connected to the first input of the first logic block and, through a serially connected single-terminator and OR logic element, to the third input of the front memory block in, the outputs of which are connected to the corresponding inputs of the decoder, the first to the second outputs of which are connected to the corresponding inputs of the second logic block, the third input of which is connected to the second input of the first logic block to the first input of the time / dp comparator and the output of the pulse generator, and the second outputs are connected to the corresponding inputs of the display and registration unit, the third output is connected to the third input of the first logic block, the first and second outputs of which are connected1 to the corresponding inputs of the block The display and registration, the fourth output of the second logic block is connected to the input of an OR element, the third and fourth outputs of the coejfector coejffflem i with the corresponding inputs of the third logic block, the first and second outputs of which are connected to the corresponding inputs of the display and recording unit, and the third output - to the second input KOMnapaTojja time intervals, the output of which is connected to the fourth input of the first logic block. Sources of information taken into account in the examination 1. Basics of building automated systems for controlling complex objects. Ed. P.I. Kuznetsova. M., 1969, 335-371. 2. Automatic control of radio electronic and electrical equipment. Ed. V.I. Shchl. M., 1972, pp. 78-168. W ... Tsapenko N.N. Measuring information systems. M., 1974, p.206 (prototype). one R ./