SU805488A1 - Analogue-digital converter - Google Patents

Description

one

The invention relates to radio engineering and is intended for use in spectrometry of ionizing measurements.

A analog-to-digital converter is known, comprising a level discriminator, a standard generator, a sampling and storage unit flj.

The disadvantage of the device is low speed.

The analog-to-digital converter is known, which contains an input device connected to the first input of the 4th drive, the output of which through the series-connected adder two memory cells is connected to its VTR9RYM input, the second input of the adder through the generator of standards, the control unit of the generator of standards is connected to the output of the master oscillator, the output of the adder through the discriminator level is connected to the input of the shift register, the output of which is connected to the input of the output block code, the logic inputs and outputs of the input device, commutation the controller, the memory cells, the level discriminator, the shift register, the code output unit and the master oscillator are connected to the control unit 2.

The disadvantage of the device is low speed.

The purpose of the invention is to increase speed.

This goal is achieved by the fact that the analog-to-digital converter containing the input device has two. memory cells, switchboard, summator, level discriminator, master oscillator, synchronization unit, reference generator unit, distribution unit, pulse counter, arithmetic unit, output unit

5 codes and a control unit, an integrator, a bit device, a block of reference duration and an additional level discriminator are entered, the input of the additional level discriminator is connected to the input of the input device and the output is connected to the third input of the control unit, the integrator input is connected to the output of the bit device and through the generator of the reference current, the block of the reference duration is connected to the output of the synchronization unit, and the output is connected to the second input of the adder and the input of the discharge device, the logical

0 whose output is connected to the corresponding logical output of the control unit.

The drawing shows a structural electrical circuit of the device.

The device contains an input device 1 that serves to change the pulse, generate a logical signal, a discriminator 2 level, switch 3, an adder 4, a discriminator 5 is even, a synchronization unit 6, a reference generator 7, a reference current unit 8, a reference current generator 9, an integrator 10 , pulse distributing unit 11, pulse counter 12, memory cells 13,14, switch input buses 15,16, control unit 17, arithmetic unit 5 to 18, code output unit 19, bit device 20. The device is intended to change the amplitude , pulses.

The converter works in the following manner.

In the initial state, the input device 1 is closed, the switch 3 is open for the input 15 and closed for the input 16, the discharge device 20 25 is closed, creating a zero level at the output of the integrator 10; memory cells 14 and 13 are open at the input, counter 12 is reset. The input signal is fed to the input device JQ 1 and to the input of the discriminator 2, which produces a logical signal. In accordance with the discriminator 2 signal, the input device 1 opens and the discharge device j 20 opens. The signal Uy enters through the input device 1, the switch 3, the adder 4 to the input of the discriminator 5, which generates a logic signal coming to the block 6. the logical signal, synchronized with the pulse of the master oscillator 7, is fed through block 8 to the input of the generator 9, from the output of which pulses are fed to the input of the integrator 10. The reference charge Qj 4S is converted by the integrator 10 at its output to the reference voltage Ugr / reverse polarity of the signal U and is fed to the second input of the summat 4, the output of which produces-JQ with the difference, T-Generator 9 produces pulses until / until the difference UxUgr-n (where n is the number of reference steps ) will not be denied. (0). The resulting n,. Compensation pulses through block 11 are recorded in the higher bits of the counter 12. The remainder Ux-Uy | -n from the output of the adder 4 enters through cell 13 to the input of cell 14, the transmission coefficient (gain) of which K is 60 ven 2, where m is the number of most significant bits of the counter is 12. After the input device 1 generates a logic signal and under the condition U - U. n 0, the second cycle of operation is started.

in which everything repeats in the same way, with the only difference that the input 15 of switch 3 opens and the input 16 closes at the output of cell 14, the output voltage of which is (Ux) 2, and the number of reference pulses is written to the next section more the minor (t) bits of the counter 12. After the end of the third cycle, the received code, according to the signal from block 17, is output through block 19 to external devices. The discharge device 20 serves to discharge the capacity of the integrator after each cycle and at the end of the conversion process. Since the compensation of the value of U does not occur to a value less than Uj, but until the value of .. "is not negative, the resulting negative value di -Uif-Ug.j is not the remainder, but an addition to the remainder t. where uUJ (is the remainder (or true remainder, respectively). Therefore, before block 19, there is an arithmetic unit 18 that converts additional codes of numbers obtained in even conversion cycles to direct codes of numbers. This process compensates for the measured value (or its amplified residue) due to the fact that it is possible to discriminate against a value relative to zero much faster. {with the same accuracy} ;, compared to discrimination, there is a relatively non-zero threshold.

Claims (1)

1. USSR author's certificate number 489219, cl. H 03 K 13/17, 1975, but. lConcHcih, StirtirK5 A.-fl-ofmau D, L. IEEE Nuck sei, -1969, Ns- (6 NePa.