SU805276A1 - Ac voltage or current controller - Google Patents

Description

(54) AC VOLTAGE REGULATOR OR CURRENT

a programmable pulse number counter, whose input is connected to the outputs of the first two coincidence circuits, and an output to the second input of the second trigger, a third coincidence circuit, the first input of which is connected to the output of a binary counter of programmed pulse numbers, and the second input to the output circuit circuit pulses of the falling edge of the third and fourth triggers, the first inputs of each of which are connected through a corresponding diode to the output of the third coincidence circuit and to the output of the leading edge pulse generator, and the second inputs of the third and fourth triggers are connected respectively to the output of a binary counter of programmed pulse numbers and the output of a falling edge pulse generator, the fourth and fifth coincidence circuits. The first inputs of each of which are connected to the output of the pulse generator, and the second with the outputs of the third and fourth triggers, respectively, of the reversible binary counter, which is the output node of the digital control unit and its inputs connected respectively with the output of the fourth and fifth coincidence circuits.

FIG. 1 shows a general scheme of current regulator; in fig. 2 - current meter; in fig. 3 - binary counter of programmatically specified numbers; in fig. 4 - raversive binary counter, switching windings; in fig. 5 - supply transformer with switching windings (2 °, 1, 2, 2, 2, 2 and 2) and the circuit of the formers of impulses of the front and rear fronts (IPF IZF); in fig. 6- time diagrams of the formation of IAP and IZP; in fig. 7 is a general voltage regulator circuit.

The contactless sensor 1 (Fig. 1) of the parameter being stabilized (in this case, the current) responds to the average current in busbar 2 of load 3. With a decrease or increase in the current in the load relative to the programmed value, the capacitance of the sensor 1 of the parameter being stabilized, which is included in phase generator RC circuit of a 4-pulse generator. With a decrease or increase in the current in the load, the frequency of the generator 4 pulses of the sound generator accordingly decreases or increases. The change in the generator frequency, expressed by the frequency of the following pulses, fixes a binary counter of 5 programmed numbers of pulses, which for a certain time must be programmed (in advance) the specified number of pulses (50, 75, 100 ...), i.e. the number of pulses (50, 75, 100 ...) in binary counter 5 a certain current is set in bus 2 of the load circuit 3. When the current in load 3 changes, the reversive binary counter 6 switches with the help of switch 7 of the phase (network) transformer winding () forms) the impulses of the middle front of the SPF and mpulsy

IZF rear edge (Fig. 5). During the course of these pulses, the current deviation in bus 2 is checked, which is carried out as follows.

The leading edge pulses of the IFP each time flip trigger 8 and Za, which allow logic circuits 9 and 9a to pass pulses from generator 4 (negative half-periods of harmonic oscillations of the generator voltage) to the input of a binary counter 5, which counts the pulses before the arrival of the back edge of the FM from the switch 7, which clears the trigger 8, and the coincidence circuit 9 stops passing pulses to the binary counter 5.

If the current in load 3 has decreased relative to the set value, then the frequency of the generator of 4 pulses has decreased and the pulse time from this generator has increased, and binary counter 5 will not have time to count the pulse from the ISF

the programmed number of pulses (50, 75 and 100) the IMF pulse will reset trigger 8, and the coincidence circuit 9 will stop applying pulses from the pulse generator to the input of binary counter 5, but trigger 8a allows the coincidence circuit 9a to pass pulses from the generator to the binary counter 5, until the counter counts the programmed number of pulses.

A biting impulse of the trailing edge transfers trigger 10, which enables the matching logic 11 to skip pulses from the generator 4 pulses to the input of the reversible binary counter 6, which will sum the number of pulses from the generator of 4 pulses proportional to the reduction of the current in the load 3 from the specified

The S, values, and the reversible binary counter 6 will thus turn on a certain number of windings, and the supply voltage will increase.

When binary counter 5 counts the programmed number, it will reset trigger 8a and thereby stop the pulses from the generator through the coincidence circuit 9a into counter 5 and also reset trigger 1 (3, which will stop the pulses from the generator to the reversing binary

5, counter b, stopping the addition of the windings of the power transformers, respectively, an increase in voltage.

If the current in the load increased relative to the set value, the frequency of the 4-pulse generator increased and the binary counter 5 counts the programmed number of pulses faster than the IZF pulse arrives, and the pulse (one) from the output of the counter 5 resets the trigger 8a and

flips trigger 12, which will allow matching logic 13 to skip pulses from the generator to the input of a reversible binary counter 6, which will then deduct a certain number of pulses proportional to the increase in current in the load, and reversible binary counter 6 will disconnect part of the transformer windings supplying the load. The supply voltage decreases, and the current in the load also decreases.

When the current in the load 3 corresponds to the programmed set value, then the binary counter 5 has time to count the programmed number of pulses before the arrival of the ISF pulse, and the matching logic circuit 14 resets the trigger 10 and 12, and the logic circuits 11 and 13 do not pass the pulse from the generator a reversible binary counter 6, and a load 3 are energized by those transformer windings that provide a programmed current.

The impulse of the leading edge of the IFP each time flushes triggers 10 and 12, flips flip-flops 8 and 8a and thereby initiates a new check for the current in load 3 at a given value in bus 2.

The accuracy of current stabilization in the load is determined by the frequency of the generator 4 pulses, the number of bits of the reversible binary counter and, accordingly, the number of switched transformer windings. The trigger, the matching logic, the binary counter and the reversible binary counter constitute the digital controller control unit.

The non-contact meter 1 (Fig. 2) is a rectangular frame winding 15 through which the direct current flows. The frame-winding is extended by straps 16 on the fixed spring 17.

When load current flows through bus 2, the winding frame (its lower arm) 15 is attracted to bus 2 with a force

F IB,

where F is the gravity force in kg; I - frame current in amperes.

I I, W

where I is the current of one turn in amperes;

W is the number of turns in the winding frame 15; In-strength magnetic field

bus current 2 in tesla; t is the length of the shoulder frame. By means of a hinge 18, a link 19 is attached to the frame 15, rotating on an axis 20. The second shoulder of the link is terminated by a plate 21 of a capacitor curved along the radius of the link shoulder. The second plate 22 of the capacitor is also bent along the radius of the shoulder of the scenes, taking into account the dielectric (air) between the plates 21 and 22 and is fixed motionless.

When the frame-winding 15 is attracted to 1 Iin 2, the plate 21 is mixed relative to the plate 22 fixed along line 23, and the capacitor capacitance changes as the area of two mutually active plates 21 and 22 changes. The frame-winding 15 moves (pulled toward tire 2) vertically with respect to tire 2 in glass 24, serving as a guide for the winding frame and as a shield for the upper arm of the winding frame. The capacitor of the plates 21 and 22 and the resistor 4a are included in the oscillating RC circuit of the generator 4 pulses and determine the pulse frequency of the generator. The trigger 25 of the binary counter 5 (Fig. 3) records the pulses from the 4 pulse generator (Fig. 1).

Matching logic circuits 26 and 27 will issue a pulse (one) if the trigger 25, 5 (2 °, 2 23 and 2) write units (2 ° -f + 2 -f 2 -f 2 75) and its high negative potential (- 9.5 C) encourage logical matching schemes. A matching logic circuit 28 will give an impulse when it is polled by software. A matching logic circuit 29 will generate a pulse if trigger 25 (2, 2 and 2) records units (22 + 2 + 26,100) and a matching logic circuit 30 triggers a pulse, if it is polled by software. Similarly, a logic matching circuit 31 will output a pulse if a trigger 25 (2, 2 and 2) records units, and a matching logic circuit 32 triggers a pulse, if it is also polled by a program or a constant negative potential, or a series of pulses (with the same generator through Tu1 1bler on the second input 50).

The shaper 33 (inhibited blocking generator used as a power amplifier), each time the logic circuits 28, 30 and 32 give 5 to its input pulses, resets all the trigger 25 (2 °, 2, 22, 2 2, 2 and 26) binary counter 5 and each time gives a pulse to the output of the counter to trigger 8, 10 and 12 and to the logic circuit 14 jj (Fig. 1). Through the generator 34 (FIG. 4) of the reversible binary counter, the matching logic circuits 35 and the adding logic 36, the generator pulses are added to the reverse binary counter 6 on the triggers 37. Through the imaging unit 38, the matching circuits 39 and the adding circuit 36 are implemented subtracting generator pulses from a reversible binary counter 6.

The primary winding 40 of the phase transformer 0 (Fig. 5) is energized by the phase (mains) voltage. Winding 41 feeds the load and is not adjustable. The windings 42-48, the number of turns of which is selected as 2 °, 2, 2 2, 2, 2 and 26, switch the trigger of the reversible binary counter 6 (Fig. 4).

The matching logic circuits 49 transmit pulses to the drivers 50 from enabling the triggers 37 of the reversing binary counter 6 (Fig. 4). Thyristors 51 include windings 42-48, and thyristors 52

disconnect these windings. If the transformer 41 is wound on an annular core, then the turns of the windings 42-48 (2, 2, 2, 2, 2, 2 and 2) correspond to the numbers 2, 1, 2, 2, 4, etc., and if the transformer winding on the W-shaped core, it is necessary to select the voltage from the windings 42-48 (2 °, 2 and 26) so that they also correspond, for example, 2 1c, 2 2b, 2 4c, etc.).

Single outputs of triggers 37 of reverse binary counter b include windings (42-48) 2 °, 2, 22 .... 26, i.e. high negative potential -9.5v) of a single output, when the trigger respectively records the unit, backs up the corresponding coincidence logic 49 that transmits the leading edge of both half-periods (positive and negative) phase (network) voltage to the shaper 50 (braked blocking oscillators used as power amplifiers), which give positive control pulses per ton The aristores 51 transmitting both voltage half-periods from the corresponding winding 42-48 (2 °, 2, 22, 2, 2, 2 and 2) and thereby increase the voltage supplying the load 3 and increasing the current. The zero outputs of flip-flop triggers 37 allow the logic circuits 49 to pass the leading edge pulses of both half-cycles to drivers 50, which drive control pulses to thyristors 52 shorting the corresponding winding 42-48 (2 °, 2, 2, 2, 2, 2 and 2) positive and negative half-periods of the supply voltage.

The boost windings 53 and 54 are symmetrical, and from the winding 53 a positive half period 55 of the phase (network) voltage 56 (Fig. B) is input to the Schmitt trigger cable 37 (Fig. 5), which produces negative rectangular pulses 58. Differentiating chain from the capacitor 59 and the resistor 60, the leading edge of these pulses is 61 - the pulses of the leading edge of the IFP and also the trailing edge of these pulses are 62 - the pulses of the trailing edge of the IST.

The emitter follower 63 and shaper 64 form powerful pulses 65 for controlling thyristors 51 and 52, which pass positive half cycles of bb with a minimum cutoff 67 (Fig. 6) into the load circuit. The emitter follower 68 and the amplifier-inverter 69 (I) form the back edge pulses of IZF 70 (Fig. 6).

A negative half period 71 (Fig. 6) is removed from the winding 54 to the input of a Schmitt trigger 72 (Fig. 5), which generates negative rectangular pulses 73 (Fig. 6). Differentiating chain of

. the capacitor 74 and the resistor 75 are separated by the leading edge of the pulse 73 (FIG. 6) —the front-leading pulse of the IFP 76, from which the emitter follower 77 and shaper 78 form pulses 79 for

thyristor control 51 and 52, which pass the negative half-periods 80 (Fig. b) with a minimum cut-off 81.

The winding 82 is removed by a reference voltage to the diode 83 (Fig. 5), equal to the sensitivity of the Schmitt trigger 72. The negative half cycles are closed through the diode 83 and the capacitor 84.

In the schemes, the input with an arrow is assumed to be pulse, and the input without an arrow is potential.

5 In FIG. Figure 7 shows a variant of the voltage regulator circuit.

Rectifier 85 (Fig. 7) converts a variable load voltage into a constant voltage of the required value to control the varicand of the pulse generator 86, which generates negative impulses and a matching logic 97. The leading edge of the positive half period of the supply voltage relieves trigger 88, which permits the matching logic 87 to pass pulses from generator 86 to the input of binary counter 89 of program voltages. At the same time, the leading edge of the positive half-cycle throws the trigger 90 and 91, which allow the logic circuits 92 and 93, to pass the pulses of the blocking generator 94 to the input of the logic circuits 95 and 96.

The pulse of the leading edge of negative half-periods resets each time

 trigger 91 and 97 and flips trigger 98. On binary counter 89, the number of pulses (6, 20 and 40) is set manually or automatically the corresponding logical matching circuit of this counter is interrogated.

0 Six pulses per half period, a supply voltage of 50 Hz corresponds to a generator frequency of 300 Hz and forty pulses per period corresponds to 2000 Hz. So, the pulse of the leading edge of the positive half cycle resets the counter 5 and flips the trigger 88, and the counter 89 starts counting the pulses of the generator 86.

Let the load voltage correspond to the required value, at which the DC voltage rectified by the rectifier 85 creates a capacitance at the variable voltage, at which the frequency of the generator 86 is, for example, 2000 Hz, which will correspond to 40 pulses in a period of 50 Hz. Toggle the switch or automatically interrogate the logic of the coincidence of binary counter 86 for 40 pulses. This means that by the arrival of the pulse of the front of the negative half-period, the -86 counter should count 40 pulses. In such

In case of coincidence of the output pulse from counter 86 and the leading edge of the negative half-cycle on the coincidence logic 99 corresponds to the fact that the load voltage is equal to that specified on the counter 8b and the output pulse of circuit 99 resets trigger 97 and 98, and the pulses of the blocking generator 94 to the reverse input binary counter 100 is not received through the matching schemes 95 and 96.

In the next period of the supply voltage, the load voltage decreases, so the frequency of the generator 96 increases, and the counter 89 counts 40 pulses faster, and by the arrival of the leading edge of the negative half-cycle, flips trigger 97, which will allow the logic circuit 95 to skip the pulses of the blocking generator 94 for summation in the reverse binary counter 100; which will add several of the windings 42-48 (2 °, P, 22, 23, 2, 2, etc.) of the transformer of the switch 7 network, and the load voltage will increase.

The leading edge of the negative half cycle will reset trigger 91 and 97, and the totalization of the blocking generator pulses 94 in counter 100 will stop.

If in the next period the load voltage has become more than necessary, then the generator frequency has decreased and the counter 89 does not have time for the arrival of the leading edge of the negative half-period to calculate the specified number 40. Then the leading edge of the positive half-cycle will throw the trigger 98, which will allow the logic circuit 96 to skip the pulses of the blocking generator 94 to subtract a certain number of pulses, proportional to the increase in voltage in the load, from the reverse binary counter 100, which turn off Some windings 42-48 (2 °, 2, 2, 2, 2, 2, etc.) of the mains transformer and the voltage of the load UK will decrease and the frequency of the generator 86 will increase to the desired value. And then the counter 89 in the next period will have time to count the given number 40 to the arrival of the leading edge of the negative half period. Thus, the pulse of the leading edge of the positive half-period of the supply voltage each time. starts checking the simplified number (6, 20, and 40) on the counter 89 to the arrival of the leading edge of the negative half-cycle of the supply voltage. Each time, the leading edge of the positive half-cycle transmits trigger 90 and 91 to allow the logic circuits 92 and 93 to pass pulses from the blocking generator 94 to coincidence circuits 95 and 96, and each time the output pulse of the counter 89 resets the trigger 88 and 96, and the forward pulse the front of the negative half-cycle resets trigger 91 and 97, which makes it possible to pass pulses from the blocking generator 94 to the input of the reversible binary counter 100 is proportional to the increase or decrease of the voltage in the load Tel'nykh predetermined value to binary counter 89 the number of pulses (B, 20, 40 and so on. d.)

Rectifier 85 with matching transformer 18 provides the permissible constant voltage to control the varicone generator 86.

Claims (2)

1. US patent number 3195038, cl. 323-25, 1970. 2. USSR author's certificate number 433458, cl. G 05 F 1/14, 1971.  2 Phys. FIG. k Fg / 2.5 FIG. AT r.220g FIG.