SU799130A1 - Analogue-digital converter - Google Patents

Description

This invention relates to a digital electrical measuring technique and can be used in the coding of wideband analog signals. The analog-to-digital converter (ADC) of a fractional coding is known, which contains a comparator, a source of a reference signal, a digital-to-analog converter, a pulse generator, and a control unit l 1. This converter has inadequate high-speed performance. Closest to the present invention is an analog-to-digital converter comprising a two-pole exponential voltage generator, comparison devices, the output of which is connected to the trigger input, a clock pulse generator, the output of which is connected to the input of the control unit, a code register and a universal switch. In this device, during the balancing process, an exponential function is used to form reference weights. The disadvantage of this converter is the low speed due to the influence of the inertia of the zero-organ and the precision voltage switch. The purpose of the invention is to increase the speed of the analog-digital converter. This goal is achieved by the fact that in an analog-to-digital converter containing a comparison device, the output of which is connected to the trigger input, a clock generator, the output of which is connected to the input of the control unit, the first output connected to the first input of the code register, the exponential current generator, The first input of the comparator device is connected to the lining of the first storage capacitor, the second lining of which is connected to the common bus, and through the selection key and the first charge key to the bus being converted and the first output of the gate device, respectively, the second input of the comparison device is connected to the storage capacitor, the second plate of which is connected to the oycle bus, and through the second charging key to the second output of the gate device, the first input of which is connected to the second output of the control unit whose third output through an exponential current generator is connected to the second input of the gating device, the second input of the code register is connected to the trigger output, the second input of the device Twa comparing chfez reset switch coupled to oydey bus. The drawing shows the block diagram of the proposed device. The analog-to-digital converter contains a key 1, a charging switch 2, 3, storage capacitors 4, 5, an exponential current generator 6, a strobe device 7, a reset key S, a clock generator 9 , control unit 1O, comparison device 11, trigger 12, register 13 codes. The first plates of the storage capacitors 4 and 5 are connected via the external keys 2 and 3 and the strobe device 7 to the output of the generator 6 of the exponential current. In addition, the first capacitor plate 4 is connected to the bus of the signal being converted via the selection key I, and the capacitor 5 is bounded by the reset key 8. The inputs of the comparison device 11 are connected to the first plates of the memorized capacitors, and its output is connected to the input of the trigger 12, which controls the charging switches. The control input of the strobe device 7 is connected via control unit 10 to the generator output 9 clock pulses. The output of the trigger 12 is connected to the numeric inputs of the register 13 code, the command input of which to the worm control unit 10 is connected to the output of the generator 9 clock pulses. The Converter operates as follows. Before the start of the next pre-phase cycle, keys 1,3 and 8 are closed, and key 2 is open. The capacitor 4 is charged before the voltage, the input voltage, and the price of the Agora 5 is discharged to zero. The ps command to start the conversion to; the I and 8 are open, and an exponentially falling current appears on the output bus of generator 6. At the first clock pulse after the transformation has started, a strobe pulse is produced, which causes the addition of a charge to the capacitor 5. equal to the area limited by the strobe pulse area of the exponentially falling current. If after this the voltage of the capacitor 5 is greater than the voltage of the capacitor 4, the comparison device 11 transfers the trigger 12 to the opposite state, but if the capacitor 4 remains charged to a larger voltage than the capacitor 5, the state of the trigger 12 does not change - no with . When the state of the trigger changes, the key 3 opens, and the key 2 closes, and in the next cycle the charge portion is received by the capacitor 4, etc. The time constant of the exponent is related to the frequency of the clock pulses so that the charge portion in each subsequent clock is half the previous one. After the end of the pulse, the state of the trigger 12 is transferred to the corresponding bit of the output register 13 of the code. The pre-phasing cycle ends after the process proceeds with a cycle of pulses equal to the number of binary bits of the code. The synchronization of the operation of all the converter nodes is performed by the control unit Yu. Due to the gating of the exponential current in the proposed converter, the key inertia effect on the linearity of the converter is eliminated, and the use of two storage capacitors makes it possible to use current switches on transistors as keys, which allows a significant increase in speed. The formula of the invention An analog-to-digital converter, a companion device, the output of which is connected to the trigger input, a clock generator, the output of which is connected to the input of the control unit, the first output of the latter is connected to the nepBtiM input of the code register, an exponential current generator, differing in that, for the purpose of rotation, the first input of the comparison device is connected to the lining of the first storage capacitor, the second lining of which is connected by a common bus, and through the switch key and the first charge ny key - the bus preobazuemogo signal and the first output trobiruyuschego device complies, the second input of the comparison device

connected to the lining of the second storage capacitor; the second lining of which is connected by an O & R bus, and through a second charging switch with a gate output, the first input of which is connected to the second output of the control unit, the third output of which is connected to the second input of the gateing device through an exponential current generator, the second input

the code register is connected to the output of three Hera; the second output of the comparison device is connected to the common bus through a reset key.

Information sources,

taken into account in the examination

1. USSR author's certificate No. 364091, KL.MN 03 K 13/17, 1967, 2. Authors of this document

N 194183O (prototype).

Bxoff 1

Yu

/ 3

-

P

/ Z

Claims (1)

Claim An analog-to-digital converter, 'containing a comparison device, the output of which is connected to the trigger input, a clock pulse generator, the output of which is connected to the input of the control unit, the first output after which is connected to the first input of the code register, an exponential current generator, characterized in that, in order to improve performance, the first input of the comparison device is connected to the lining of the first storage capacitor, the second lining of which is connected to the common bus, and through the sampling key and the first charging _key - from the buses th converted signal n th first output of the gating device, respectively, the second input of the comparison device 799,130 'is coupled to plate ⁵ of the second storage capacitor; the second lining of which is connected to the common bus, and through the second charging key, to the second output of the gating device, the first input of which is connected to the second output of the control unit, the third output of which is connected through the exponential current generator to the second inputs of the gating device, the second input of the code register connected to the trigger output, the second “J” input of the comparison device through the reset key is connected to the common bus.