SU798834A1 - Device for control of redundancy of information in computing complexes - Google Patents

Description

The drawbacks of the device are a decrease in reliability due to the need to introduce flexible addressing, a decrease in the utilization ratio of the equipment due to the time spent on the redistribution of memory modules by processors during operation.

The purpose of the invention is to increase the reliability and utilization of equipment.

The goal is achieved by the fact that the device for managing the reservation of information in computer complexes, containing the operation register, the output of which is connected to the input of the decoder, the recording control unit, the output of which is connected to the first controlling output of the device, the first element AND the outputs of which are connected respectively to the inputs of the first element AND, the inputs of the eighth element OR are connected respectively to the first and second inputs of the device, the inputs of the second element OR the connection respectively Actually with the third and fourth inputs of the device, the trigger, the third and fourth elements OR, the second and third elements AND are entered, the first input of the third element OR connected to the first output of the decoder, the second output of which is connected to the second input of the third element OR and a single trigger input, the output of the third element OR is connected to the first input of the recording control unit, the second input of which is connected to the output of the fourth element OR, and the output is connected to the first input of the second element AND, the second input of which is connected to the single output of the trigger, the output of the second element AND is connected to the second control output of the device, the zero input of the trigger is connected to the output of the first element OR, the inputs of the third element AND are connected respectively to the zero output of the trigger and the output of the second element OR, the outputs of the first and third elements And they are connected respectively to the inputs of the fourth element OR.

By introducing the above-mentioned additional elements and links into the structure of the complex processors, a special operation is entered for the operation, Recording with a reservation, when executed: and which the information is being backed up. When performing the remaining Operations of such a reservation, it is not performed. Due to this, when developing software for a complex, it is possible to write simultaneously to both groups of memory modules only that information necessary for organizing the interaction of processors and continuing the operation of the complex in case of failure of individual memory modules.

In contrast to the known devices, for short-term access of the processor to the backup memories from the device, it is not necessary to perform additional operations of connecting the processor to these devices, or to include in the complexes additional equipment providing

Q constant access to each of the processors to the reserved areas of the general RAM.

FIG. 1 shows a block diagram of a digital computing complex of FIG. 2 - structural

 device schema for managing backup information.

The complex includes the first processor 1, the second processor 2, the memory modules 3 of the first group and the modules

0 4 memories of the second group. Processor 1 is connected to memory modules 3 and 4 by code lines 5, and processor 2 is connected to memory modules by code lines 6. Processor 1 and

5 processor 2 is associated with modules 3 and 4 with memory busses record 7 and 8, as well as end of record 9 and 10.

A device for managing backup information is included in

Q composition of the digital computer complex.

The information management register includes the operation register 11, the encoder 12 operations connected to it, the record management unit 13 and the trigger 14, which are used for the operational management of information reservation.

The inputs of the operation register are connected to the outputs of the command recorder (on

0 drawing command register not shown).

The first input of the recording control unit 13 is connected to the output of the OR-15 element, the first input of which is connected by a connection 1.6 to the output of the decoder 12 operations corresponding to the operation and recording. The second input element OR 15 is connected by a link 17 with another output of the decoder 12 operations, corresponding to the operation Write

0 with redundancy, as well as with a single input of the trigger 14. The output of the recording control block 13 is connected to the first input of the AND 18 element and the first control output of the device, which, in turn, is connected to the bus 8 Writing memory modules. The second input of the And 18 element is connected to the single output of the trigger 1. The output of the And 18 element is connected to the second control output of the device. The second control output of the device is connected to bus 7 Writing memory modules. The second code of the recording control unit 13 is connected to the 5-OUT of the element OR 19.

The inputs of the element OR 19 are connected to

5 outputs of the two elements And 20 and 21.

The first input element And 20 is connected to the zero output of the trigger 14. The second input element And 20 is connected to the first input element And 21 and the output element OR 22. The second input element

And 21 is connected to the zero input of the trigger 14 and the output of the element OR 23. The inputs of the element OR 22 are connected to the first and second inputs of the device. The inputs of the element JiJiIi 23 are connected to the third and fourth inputs of the device. The first, second and third., Fourth devices are connected to buses 9 and 10. The end of the recording of the memory modules, respectively.

The code lines 5 and 6 of the digital computing complex are transmitted to all the memory modules of the address and the recorded information. The signal that permits the recording of information transmitted via code lines 5 and b is the recording signal transmitted on buses 7 and 8 from the processor. The termination of writing information to the memory module is indicated by a signal output on buses 10 End of recording from the memory modules to the processor.

The memory modules have address selectors, which are used to record the coincidence of the mathematical addresses assigned to the modules and the addresses transmitted via code lines. In addition, the memory modules have local control devices that organize the alternate processing of requests from two processors. memory modules in different groups are assigned the same mathematical addresses.

The main mode of operation of the complex is the simultaneous solution of various tasks under the control of the dispatching room, performed on one of the processors. In the course of operation, in memory modules with the same mathematical addresses located in different groups, common information zones are formed, containing data necessary both for simultaneous execution of tasks by two processors and for storing information in case of a fault: one of the modules memory If one of the memory modules fails, one processor (any) continues to perform the full list of tasks using the information stored in the memory module of another group. Tasks in the backup mode of operation are performed less frequently than in general, or selectively, not in full force, only the most important ones.

Shared information zones are formed when a backup operation is performed in the processor, which is used by the programmer to record information in two groups of memory modules.

The remaining memory zones are formed when the processors perform other operations, are individual for each of the processors and do not coincide in the two groups of modules. The read access passes from each processor only to the corresponding group of memory modules.

Operation: The recording is performed in the complex as follows.

0

After setting the operation code on the register 11. Of operations, the output of the decoder 12 operations on communication 16 receives a signal which through the OR 15 element is fed to the input of the block

s 13 write controls.

When performing an operation. Record with redundancy from the output of the decoder 12 operations psg communication 17 receives a signal at the single input of the trigger 14 and to the input of the element OR 15. Block 13

0 recording control is triggered by a signal from the output of the element OR 15, organizes the transfer of information and addresses from the processor registers to the code line, generates signals Record

5 to bus B, arriving at the memory modules of the group corresponding to the processor, and Recording signals through an And 18 element, which is open to potential from a single output of the trigger 14, to the busses 7,

0 coming to another group of memory modules. .

This block organizes the transfer of information and addresses from the processor registers to the code trunk (signals, not shown in the drawing) and with a delay generates a signal on bus 8, which goes to the memory modules of the group corresponding to the processor. Signal The end of the recording from the memory module that supplied the information goes through bus 10 to the processor to the input of the element OR 22. From the output of the element OR 22 through the element AND 20, to the second input of which the resolving potential comes from the zero start of the trigger 14. Signal from the output of the element AND 20 is fed to the input of the element OR 19 and from its output to the second input of the recording control unit. Record management unit 13 after

O this organizes the transition of the processor to the next operation.

with

After completion of the recording, signals appear at the memory modules of both guop. End of recording at the inputs of the elements

5 OR 22 and 23. Signals from the outputs of the elements OR 22 and 23 are fed to the input of the element AND 21. If the recording has passed in the memory modules of both groups, the output of the element 21 is the signal

O which then goes through the element

OR 19 to the input of the recording control unit 13. The trigger 14 is reset to the initial state by a signal from the output of the element OR 23. The record block 13 ynt5 records the transition.

processor to perform the following operations.

In a digital computing complex using the described device, the flexibility of managing the composition of the backed up information is increased, thereby increasing the functionality of the complex and its reliability, more fully utilizing the physical storage capacity of the complex (increasing the utilization rate of equipment).

Claims (2)

1. US Patent No. 3838261, cl. 235-153 A F (G 06 F 15/16), published. 1974. - 2. US patent number 3905023, cl. 235-153 LC {G On F 11/06), published. 1975 (prototype).