SU794764A1 - Digital demodulator of frequency telegraphy signals - Google Patents

Description

one

The invention relates to telecommunications and can be used to transmit discrete information data. A digital demodulator of frequency telegraphy signals is known, comprising a key block, a decoder, an operating frequency detection unit, a frequency divider, a trigger unit, two limiters, a differentiation circuit, an voice filter and a reference oscillator, the output of which is connected to the first limiter, the output of which is connected to the first the input of the frequency divider, the second input of which is connected to the first output of the start-up unit, the second output of which is connected to the first input of the working frequency determination unit and the first input of the decoder, the second input which is connected to the first output of the frequency divider, the second output of which is connected to the second input of the operating frequency detection unit, the output of which is connected to the first output of the key block, the second input of which is connected to the first output of the decoder, the second output of which is connected to the third input of the key block, besides , the output of the bandpass filter is connected to the input of the second limiter, the output of which is connected to the input of the differentiating circuit, the output of which is connected to the input of the starting block 1.

However, in a known digital demodulator, there is a temporal distortion in the bits of the received combinations, determined by the presence in the device

Comparison unit, low pass filter and decision circuit.

The purpose of the invention is to reduce temporal distortion of signals.

To do this in a digital demodulator,

containing a block of keys, a decoder, a block for determining the operating frequency, a splitter, a trigger, two limiters, a differentiating circuit, a band-pass filter and a reference oscillator, an output

which is connected to the input of the first limiter, the output of which is connected to the first input of the frequency divider, the second input of which is connected to the first output of the start-up unit, the second output of which is connected to the first input of the working frequency determination unit and the first input of the decoder, the second input of which is connected to the first output frequency divider, the second output of which is connected to the second

the input of the operating frequency detection unit, the output of which is connected to the first input of the key block, the second input of which is connected to the first output of the depyfrater, the second output of which is connected to the third input of the key block, in addition, vy3,

the stroke of the bandpass filter is connected to the input of the second limiter, the output of which is connected to the input differential of the circuit, the output of which is connected to the input of the start-up unit, and a control unit, a deciding unit and a discharge determining unit are entered. the parcel, the first input of which is connected to the output of the key block, the second input of the block for determining the discharge of the received parcel is connected to the first output of the control unit, the second output of which is connected to the first input of the decision block and to the first the block of the formation of received information, the third output of the control unit is connected to the second input of the block of formation of bits of the received information and the second input of the decision unit, the fourth output of the control unit is connected to the third input of the block of formation of bits of the measured information, the fourth input of which is connected to the first output of the deciding unit and with the first input of the control unit, the fifth input of the block of formation of bits n |) of the information to be removed is connected to the second output of the decision block n with the second input of the block The control unit, the third input of which is connected to the fourth input of the key block and the first output of the bit formation block of the received information, the fourth input of the control block is connected to the third output of the deciding block, the fifth input of the control block is connected to the second output of the bit shaping block information and with the fifth input of the key block, the sixth input of the control unit is connected to the first output of the block of determining the discharge of the received parcel, the second output of which is connected to the third input of the decision unit, the third The output of the unit for determining the bit of the received parcel is connected to the seventh input of the control unit, while the output of the first limiter is connected to the fourth input of the decision block, in addition, the block for determining the bit of the received parcel is made in the form of two decoders, trigger, counter, element I, the first input which is connected to the first input of the trigger, the first output of which is connected to the second input of the element I, the output of which is connected to the first input of the counter, the second input of which is connected to the second output of the trigger, the output of the counter connected to the inputs of the decoders, while the first input of the AND element, the second input of the trnger and the outputs of the decoder are respectively the inputs and outputs of the entire block, in addition, the decision block is made in the form of three decoders, two counters, an OR element, an AND element and two triggers, the output of the first t |) igger is connected

four

to ne) the input of the input element I, the output is connected to the first input of the element OR, the second input of which is connected to the first input of the second trigger and the first input of the first counter, the second input of which is connected to the output of the second trigger, the output of the first counter is connected to the input of the first the decoder, the output element OR is connected to the first input 1 of the second counter, the output of which is connected to the input of the second and third decoders, the output of the second decoder is connected to the first input of the first counter, and the inputs of the first trigger, second input Alone second .5 th trigger, second inputs of the And element and the second counter, as well as the outputs of the decoders are respectively the I / O and the outputs of the entire unit, in addition, the control unit is made in the form of three OR elements, a trigger and three And elements, the output of the first element And it is connected to the first input of the first OR element, the second input of which is connected to the output of the second AND element, and to the first input of the second OR element, the second input of which is connected to the third input of the first OR element, to the output of the third OR element and to the first input three the outgrower, the output of which is connected to the first input of a third gQ of its element AND, the second input of the trigger is connected to the first input of the second element AND, the output of the third element AND is connected to the first input of the third element OR, and two inputs of the first element AND the input of the third element OR, the third and fourth inputs of the first element OR, the first and second inputs of the second element AND, and the outputs of the first and second element OR, Q of the first element AND are the inputs and outputs of the whole unit, moreover, the form block No bits of received information are made in the form of two elements AND, element OR, two 5 triggers, the first output of the first trigger is connected to the first input of the first element AND, the second input of which is connected to the first input of the second element And, the second input of which is connected to the second Q output the first trigger, the output of the second element AND is connected to the first input of the OR element, the output of which is connected to the first input of the second trigger, the second input of which is connected to the output nejjBoro r of the AND element, and the inputs nepBoix) of the trigger The OR inputs, the input of the second element, AND, and the first and second outputs of the first trigger are, respectively, the inputs and outputs of the entire unit.

The drawing shows the structural electrical circuit of the proposed demodulator.

The demodulator contains a reference generator 1, the first cutter 2, the frequency divider 3, the band-pass filter 4, the second limiter 5, the differentiating circuit 6, the start block 7, the working frequency determining block 8, the decoder 9, the key block 10, the received discharge determining block 11 parcels, a decisive block 12, a block 13 of control and a block 14 of forming bits of the received information.

Block 11 contains the counter 15, the element And 16, the trigger 17 and the decoders 18 and 19. Block 12 contains the counters 20 and 21, the decoders 22 and 23, the first trigger 24, the element OR 25, the element And 26, the second trigger 27 and the third decoder 28 .

Block 13 contains elements AND 29, 30 and 31, trigger 32 and elements OR 33, 34 and 35.

Block 14 contains the triggers 36 and 37, the elements And 38 and 39 and the element OR 40.

The demodulator works as follows.

Signals entering the demodulator input are filtered in filter 4 and are limited in limiter 5.

The rectangular sequence of frequency-manipulated pulses from limiter 5 is fed to circuit 6. From the output of circuit 6, short pulses corresponding to the zero-crossing of input signals go to block 7.

The unit 7 generates, on signals from circuit 6, pulses of the beginning of the division of the frequency of the reference oscillations of generator 1, limited in limiter 2 by divider 3, and polling pulses of the decoder 9 and unit 8, following the frequency period of the signal acting at the input. The frequency division start pulses immediately follow the interrogation pulses and the divider 3 is reset to its initial state. After the start of the green pulse, divider 3 begins to divide the frequency of the reference oscillations. The division process continues until the arrival of the interrogation pulse, i.e., a time interval equal to the frequency period of the input signal.

If at the input of the demodulator there are signals corresponding to a single and zero discharge of the parcel with frequencies in the working frequency band of the demodulator, then for periods of input signals, divider 3 will accept such conditions that block 8 will use it and polling pulses block 7 will generate signals that open block 10, and the decoder 9 will decipher the state of the divisor class 3 and the polling signal from the block 7 with signals at its outputs.,

Under the action of a single bit of a parcel on the demodulator input on one and when a zero bit signal acts on the other outputs of the decoder 9, pulses appear, the number of which is equal to the number of characteristic periods

frequencies per bit combinations.

In the initial state in block 11, the counter 15 is held in the zero state by a single potential supplied to its installation input from the inverse output of the trigger 17, and the main input of the counter 15 is closed by supplying a zero potential from the control input element And 16 that trigger output 17. The decoders 18 and 19 are programmed to decipher the states of counter 15, corresponding to the single and zero discharge ratios, respectively, and depending on the transmission rate of the information (on the length of the send bits).

In block 12, the counter 20 is held in the zero state by a single sweep sent to its installation input through the OR 25 element from the output of the AND 26 element, the inputs of which are fed to the single potentials from the inverse outputs of the flip-flops 17 and 27. The decoders 22 and .23 are programmed the decoding of the states of the counter 20, modified by the signals from the output of the first limiter 2, the corresponding indications of the presence and end of the bits of the combinations in accordance with the speed of information transfer. The counter 21 is held in the zero state by a single potential supplied to its setup input from the inverse output of the trigger 24. The programmable decoder 28 is programmed to desh1fraction the states of the counter 21, modified by signals from the decoder 23 corresponding to the sign of the end of all received information depending on selected baud rate.

In block 13, the trigger 32 is in the initial state, in which a single potential is located at the inverse output of the trigger 32.

In block 14, the flip-flops 36 and 37 are in the initial states, in which the unit potentials are at the inverse outputs, while the unit potential from the inverse output of the trigger 36 nodan to the auxiliary input of the block 10 and connects the output of the decoder 9, to which io are the pulses corresponding to the unit bits of the parcels to the cc of the block 11.

When postunlenny to the input of the demodulator signal with a characteristic single-bit frequency, the pulses from the output of block 10 are sent to the inlet of block 11. Trigger 17 from the first pulse changes its state and resolves the counters 15 and 20. As a result Two processes begin - the identification of the bits of the pools and the formation of signs of the received parcels. When the number of pulses arrives at the input of block 11, which sets the counter 15 to the state decoded by the decoder 19, the signal from the output of the decoder 19, the trigger 32 of the block 13 will change the state and thereby ensure the processing of a single bit. Upon further receipt of pulses at the input of block 11, the counter 15 is set to such a state in which the decoder 18 generates a signal that, through the element 29, goes to the triggers 27, 36 l through the element OR 34 to reset the trigger 17. The installation of the trigger 27 will ensure the operation of the block) 2 on the continuation of the whole parcel, and the trigger 36 switches the block 10, sets the trigger 37 to one state through the AND 38 element according to the signals of the combination discharge from the decoder 22, unlocking the AND 30 element and locking the AND 29 element.

When a zero-bit signal arrives at the input of the demodulator, block 11 functions in the described manner, but now the signal from the decoder 19 through AND 30, the OR 34 element is fed to the initialization of the trigger 17 and the trigger 36, which ensures that the zero state is set the trigger 37 through the element AND 39 and the element OR 40 at the signal of the sign of the discharge of the parcels from the decoder 22, switching the block 10 and unlocking the element And 29 and locking the element And 30.

When forming the sign of the end of the discharge, the end of discharge signal from the output of the decoder 23 through the OR element 34 causes the block 11 to return to its initial state, set the counter 20 to the zero state through the OR element 25, and enable the counting of the number of bits of the parcels by the counter 21 by setting a trigger 24

In the manner described above, demodulation of bits of received parcels is performed. The formation of bits of received parcels is completed either by the last burst of parcels, or by the generated signal by the decoder 28 supplied through the OR 35 element to the initial state of the blocks 12, 13 and 14, and through the OR 34 element to the initial state of the block P.

If a signal of the sign of the discharge of the parcels by the decoder 22 is generated, provided triggering trigger 17 is noisy, this signal through the AND 31 element and the OR 35 element will reset all the demodulator nodes.

Introduction to the demodulator of a unit for determining the bit of a received parcel, its block, as well as control circuits and shaping the bits of received information and the presence of manual or automatically programmable decoders completely eliminates the temporal distortion of bits of received packets.

Claims (5)

1. Digital demo.: 1.ulto1) signals of a frequency telegraph, containing a key block, a decoder, a working frequency determination block, a frequency divider, a trigger block, two limiters, a differential circuit, a band-pass filter and a reference oscillator, an output which is connected to the input of the first limiter, the output of which is connected to the first input of the frequency divider, the second input of which is connected to the first output of the starting block, the second output of which is connected to the first input of the working frequency determination unit and the first input of the decoder, the second input to The output of the frequency divider, the second output of which is connected to the second input of the working frequency detection unit, is costly connected to the nejJBbiM, the KOTOpoio output is connected to the first input of the key block, the second input of which is connected to the first output of the decoder, the second output of which is connected to the third input of the key block, in addition, the output of the bandwidth is connected to the input of the second limiter, the output of which is connected to the input of the differentiating circuit, the output of which is connected to the input of the trigger unit, characterized in that, in order to reduce the time signals, a block for forming bits of received information, a control block, a deciding block and a block for determining the discharge of the received parcel, the first input of which is connected to the output of the key block, the second input of the block of determining the discharge of the received parcel, are connected to the first output of the control block, the second output which is connected to the first input of the decision block and to the first input of the block of formation of bits of received information, the third output of the control block is connected to the second input of the block of formation of bits of received information to the second input of the decision block, the fourth output of the control block is connected to the third input of the discharge bits formation unit, the fourth input of which is connected to the first output of the decision block and the first input of the control block, the fifth input of the bits block of the received information is connected with the second output of the decision block and with the second input of the control block, the third input of which is connected to the fourth input of the key block and to the first output of the block of formation of bits of the received information the fourth input of the control unit is connected to the third output of the decision unit, the fifth input of the control unit is connected to the second output of the block of formation of the received information and the fifth input of the key block, the sixth input of the control unit 9 It is connected to the first output of the block for determining the discharge of the received parcel, the second output of which is connected to the third input of the decision unit, the third output of the block for determining the discharge of the received parcel is connected to the seventh input of the control unit, while the output of the first limiter is connected to the fourth input of the decision box. 2. A demodulator according to claim 1, characterized in that the block for determining the discharge of the received parcel is made in the form of two decoders, a trigger, a counter, an element, whose first input is connected to the first input of a trigger, the first output of which is connected to the second input of the element The output of which is connected to the first input of the counter, the second input of which is connected to the second output of the trigger, the output of the counter is connected to the inputs of the decoders, the first input of the And element, the second input of the trigger and the output of the decoders are respectively the inputs and output E whole block. 3. A demodulator according to claim 1, characterized in that the decision block is made in the form of three decoders, two counters, an OR element, an AND element and two triggers, the output of the first trigger is connected to the first input of the AND element, the output of which is connected to the first input of the E OR, the second input of which is connected to the first input of the second trigger and the first input of the first counter, the second input of which is connected to the output of the second trigger, the output of the first counter is connected to the input of the first deflector, the output of the OR element is connected to the first input of the second account The output of which is connected to the input of the second and third decoders, the output of the second decoder is connected to the first input of the first counter, the inputs of the first trigger, the second input of the second trigger, the second inputs of the And and second counters, and the outputs of the decoders are respectively inputs and outputs whole block. 4. A demodulator according to claim 1, characterized in that the control unit is made in the form of three elements OR, a trigger ten and three elements And, the output of the first element And is connected to the first input of the first element OR, the second input of which is connected to the output of the second element AND and with the first input of the second OR element, the second input of which is connected to the third input of the first OR element, with the output of the third OR element and with the first trigger input, the output of which is connected to the first input of the third AND element, the second trigger input is connected to the first input of the BTOpoiO AND element , the output of the third element And is connected to the first input of the third element OR, and the two inputs of the first element AND, the second input of the third E.And, the second input of the third element OR, the third and fourth inputs of the first element OR, the first and second inputs of the second element AND, and the outputs of the first and second element, the first element AND, are respectively the outputs of the whole block. 5. Demodulator tor. p. 1, characterized in that the block of formation of bits of the received information is made in the form of two AND elements, an OR element, two triggers, the first output of the first trigger is connected to the first input of the first AND element, the second input of which is connected with the first input of the second element AND, the second input of which is connected to the second output of the first trigger, the output of the second element AND is connected to the first input of the OR element whose output is connected with the first input of the second trigger, the second input of which is connected to the output of the first element AND, the inputs of the first trigger, the second and third inputs of the OR element, the input of the second element AND, the first and The second outputs of the first trigger are respectively the inputs and outputs of the entire unit. Information sources, 45 taken into account in the examination 1. USSR author's certificate No. 545091, cl. And 04L 27/10, 1974 (nroto50 type).