SU794752A1 - Binary signal generator - Google Patents

Description

with the output of the first element OR, the switch output is connected to the first inputs of the first and second counters, the second inputs of which are connected to other switch outputs, the second output of the synchronization unit is connected to the ne; the first input of the first key, the output of which 11 is connected to the first input of the recording distributor and to the first input of the read distributor, the corresponding output of the distributor counter is connected to the second input of the write distributor, the outputs of which through the series-connected block of recording elements, the element block in the buffer memory and the block of read elements are connected to the inputs of the corresponding second and third OR, the outputs of which are connected to the inputs of the output trigger, the corresponding output of the write distributor is connected to the second input of the first key, the other output of which is connected to the second input of the read distributor whose outputs are connected to other inputs of the readout unit, the second and third keys, the fourth and fifth OR elements, the noise analyzer, the input analyzer, the write cycle correction unit and, - a transponder block, a block for checking the phase of the recording signal, a block for determining the sign and shift amount of the recording signal, and a block for determining the input signal shifter, the outputs of the first and second counters are connected to the first inputs of the second and third keys, respectively, whose outputs are through the fourth and fifth OR elements are connected to other inputs of an addition unit and a subtraction unit, respectively, the output of the first OR element is connected to the inputs of the noise analyzer and input analyzer, the outputs of which are connected to the second and three To the inputs of the second and third keys, the corresponding output of the read distributor is connected to the first inputs of the phase check block of the recording signal, the block of determining the sign and magnitude of the shift, the write signal and the block of determining the sign of the input shift, the outputs of which are connected to the first input of the cycle correction block through the decisive block recording, the output of the phase check signal of the recording signal is connected to the second input of the write cycle correction block, whose outputs are connected to the other inputs of the fourth and fifth elements of the ILR1, the output of the first The OR element is connected to the second input of the input signal definition block, the corresponding input of the recording element block is connected to the second inputs of the signal definition block and the value of the signal shift and the recording signal phase check block, the third input of which is connected to the noise analyzer output.

The drawing shows a structural electrical circuit of the proposed regenerator.

The binary signal regenerator contains asynchronous receiver 1, synchronization unit 2, master oscillator 3, first element OR 4, subtraction unit 5, addition unit 6, distribution counter 7, switch 8, first 9 and second 10 counters, second 11 and third 12 elements OR, the first 13 and second 14 keys, the noise analyzer 15, the input signal analyzer 16, the recording cycle correction block 17, the decisive block 18, the recording signal phase checking block 19, the recording signal shift sign and offset value block 20, the shift sign detection block 21 input signal, third key 22, write distributor 23, block 24 of write elements, SO block of 25 elements of buffer memory, block of 26 read elements, fourth 27 and fifth 28 OR elements, read distributor 29, output trigger 30.

25 Regenerator binary signals works as follows.

The binary information signal is fed to the input of the asynchronous receiver i, at the outputs of which, depending on the output of the 30th signal, pulses are formed corresponding to the boundaries of the elementary premises. The generated pulses are fed to block 24 to store the input information, as well as to adjust the clock synchronization system. The pulses arrive at the input of block 2. From the output of block 2, through blocks 5 and 6, the pulse signal with a frequency exceeding 4 times the clock frequency / o. The distribution counter 7 is calculated for four outputs and at the same time performs the function of a conventional counter for four, so the signal from the fourth output of the distribution counter 7 5 has a clock frequency and controls the operation of the distribution valve 23.

In order to avoid errors, when the amplitude of oscillations of the input signal, together with the noise fluctuations of the phase of the parcel boundary, is half the duration of the parcels, the phase of the input signal is monitored with respect to the reference signal, which is a fourfold clock frequency, g removed from the output of block 2, and the change in accordance with the direction and speed of oscillations of the phase of the signal at the input of the counter-distributor 7, which automatically leads to a change in the phase of the signal at the input of the counter-distributor 7. When o cachapa presence of signal at the input of the regenerator is not fluctuating phase position of parcels boundaries corresponds to the middle period of the clock pulse sequence 5 output from the fourth

distribution counter 7. The real noise fluctuations of the boundaries of the parcels are not large and are in the ± jLTo

which corresponds to the second and third states of the distribution counter 7.

This does not lead to a change in the phase of the signal at the output of the distribution counter 7. The distribution valve 23 is controlled by a signal from the fourth output of the distribution distributor 7.

If there are input swings to prevent errors. When recording input information, the phase of the input signal is monitored with respect to the reference signal, and the phase of the recording signal is changed by ± 1 / 4to in accordance with the direction and swinging phase of the input signal. This is accomplished with the help of blocks 5 and 6, counter-distributor 7, switch 8 and counters 9 and 10. Thus, the probability of false reception of information is reduced and high clock synchronization stability is achieved with fast swings in the phase of the input signal.

The operation of the regenerator in the following possible states of the input signal:

changing the highly noisy input signal a-normal;

slight (until then) oscillation and fluctuation of the front of the input signal;

slow significant (more TO) shifts of the fronts of the input signal;

sharp for one or two parcel phase jumps of the input signal of more than 1/2 To.

Analyzers 15 and 16, constantly analyzing the input signal, issue commands that signal the arrival at the input of the noise generator (a strong noise signal) or a normal input signal. Analyzers 15 and 16 are a set of counters, to the input of which the edges of the input signal are applied. The analysis of the noise or the input signal is based on the real normal law of the distribution of the fronts of the input sigial in the zone of their most likely occurrence. In the case of noise, the pulse-command closes the keys 14 and 22. This eliminates the chaotic adjustment of the recording signal by the noise fronts. In addition, the same pulse signals the need for checking the phase of the recording signal. In the case of a phase shift of the recording signal, which is determined by block 19, a command is received at block 17 to correct the recording signal. It is thereby prepared to record the input information in the event it arrives. Block 17 is a generator of a certain number of pulses for adding them to a sequence of pulses arriving at the input of a distribution counter6

Letter 7, or subtraction from this sequence. Their number depends on the amount of correction required to restore the phase of the recording signal. The amount of write signal drift relative to a highly stable readout signal is constantly determined by block 19. With a normal input signal, analyzer 16 delivers a command on keys 14 and 22, opening them and allowing them to monitor the input linkage signals, unhindered skip addition or subtraction pulses on the inputs of blocks 5 and 6.

When random fronts of the input signal fluctuate or their slight slow shifts, the phase of the recording signal is adjusted using the distributor counter 7, the switch 8 and the counters 9 and 10 by adding or subtracting one pulse in blocks 5 and 6 with the displacement of parcel boundaries more than 1 / 4To . Thereby, the recording signal is tracked behind the shifting inputs. In blocks 20 and 21 (with the write cycle), the direction of the front edge of the input signal and the phase adjustment of the write signal relative to the highly stable read signal are determined. And the swinging phases of the input signal can reach a value exceeding the resolution of the buffer memory, i.e. the possible number of adjustments will be used, which is determined by the capacity of block 25 and the adjustment pag (capacity of counter-distribution 1). In this case, decision block 18 issues a command to block 17 to restore the write cycle, thereby eliminating possible failures in the cycle.

With sharp tripping phase of the fronts of the input cngnal by more than 1/2 TO in one or two premises errors may occur when the signs of the shift of the fronts of the input signal and recording signal do not coincide as a result of incorrectly determining the signal records in the system switch 8, counter-distributor 7, counters 9 and 10. As soon as the recording signal moves one adjustment step and the sign of the adjustment does not coincide with the sign of the input signal shift, immediately after incoming pulses-commands from blocks 20 and 21 the block 18 ODA cases is the direction of the recording signal and its correction value necessary for eliminating glitches on cycle. At the command of block 18, block 17 outputs the required number of pulses of addition or subtraction to the inputs of blocks 5 or 6, thereby immediately changing the sign of adjusting the recording, not only the sign of adjusting the recording will change (according to the offset of the sleeper), but the phase correction will also be necessary. misalignment of the recording signal and the input signal. Further adjustment will be made in accordance with the possible input signal conditions.

Claims (1)

Invention Formula A binary regenerator containing an asynchronous receiver, the outputs of which are connected to the inputs of a block of recording elements and through the first element OR to the first input of the synchronization unit, the output of the master oscillator is connected to the input of the asynchronous receiver and to the second input of the synchronization unit, the first output of which is through serially connected subtractors , the addition unit and the distribution counter are connected to the first inputs of the switch, the second inputs of which are connected to the output of the first OR element, the output of the switch is Yuchen to the first inputs of the first and second counters, the second inputs of which are connected to other outputs of the switch, the second output of the synchronization unit is connected to the first input of the first key whose output is connected to the first input of the write distributor and the first input of the read distributor, the corresponding output of the distributor counter is connected to the second input of the recording distributor, the outputs of which are connected via a serially connected block of recording elements, a block of buffer memory elements and a block of reading elements The corresponding inputs of the write distributor are connected to the inputs of the corresponding second and third OR elements, the corresponding output of the write distributor is connected to the second input of the first key, the other output of which is connected to the second input of the read distributor, the outputs of which are connected to other inputs of the block of reading elements, differing from that, in order to increase the credibility receiving binary signals, the second and third keys, the fourth and fifth elements OR, the analyzer of the chuma, the analyzer of the input signal, the write cycle correction block, the deciding unit, the block of checking the phase of the recording signal, the block of determining the sign and shift of the recording signal, and the block of determining the sign are entered shift the input signal, while the outputs of the first and second counters are connected to the first inputs of the second and third keys, respectively. The outputs of which through the fourth and fifth elements OR are connected to other inputs of the corresponding block are added nor and the subtractor unit, the output of the first element OR is connected to the inputs of the analyzer of the skum and the analyzer of the input signal, the outputs of which are connected to the second and third inputs of the second and third keys, the corresponding output of the read distribution distributor is connected to the first inputs of the recording phase check block, the sign determining unit and the shift value recording signal and block definition the sign of the shift of the input signal, the outputs of which through the decision block are connected to the first input of the write cycle correction block, the output of the write signal phase check block is connected to the second the input of the write cycle correction block, whose outputs are connected to other inputs of the fourth and fifth OR elements, the output of the first OR element is connected to the second input of the sign determining unit the input signal shift, the corresponding input of the block of recording elements is connected to the second inputs of the block for determining the sign and magnitude of the recording signal shift and the recording signal phase checking block; which entrance with an exit of the analyzer of Shuma Sources of information taken into account in the examination 1. USSR author's certificate in application No. 2535144 / 18-09, cl. H 04 B 3/02, 1977 (prototype).