SU790187A1

SU790187A1 - Pulse shaper

Info

Publication number: SU790187A1
Application number: SU792718404A
Authority: SU
Inventors: Валерий Евгеньевич Гусев; Геннадий Иванович Крамков
Original assignee: Предприятие П/Я Г-4665
Priority date: 1979-01-29
Filing date: 1979-01-29
Publication date: 1980-12-23

Description

Изобретение относится к импульсной технике и может быть использовано в устройствах цифровой техники.The invention relates to a pulse technique and can be used in digital technology devices.

Известен формирователь импульсов, состоящий из двух элементов И-НЕ, ин- 5 вертора и интегрирующей RC-цепи, причем два элемента И-НЕ включены по схеме триггера, а выход одного из : них соединен со входом другого через последовательно соединенные инвертор 10 и интегрирующую RC-цепь £1J .A pulse shaper is known, consisting of two AND-NOT elements, an inverter 5 and an integrating RC circuit, and two AND-NOT elements are included according to the trigger circuit, and the output of one of them is connected to the input of the other through a series-connected inverter 10 and an integrating RC chain £ 1J.

Недостатком данного формирователя является нестабильность длительности выходных импульсов при длительности сигнала логического нуля на входе 15 формирователя, меньшей времени заряда конденсатора от уровня логического нуля до уровня логической единицы, и полное несрабатывание формирователя при длительности сигнала логического 20 нуля на входе, меньшей времени заряда конденсатора от уровня логического нуля до порога переключения элемента И-НЕ триггера.The disadvantage of this shaper is the instability of the duration of the output pulses when the duration of the logic zero signal at the input 15 of the shaper is less than the charge time of the capacitor from the logic zero level to the level of the logical unit, and the complete failure of the shaper when the duration of the signal is logical 20 zero at the input is less than the charge time of the capacitor from the level logical zero to the switching threshold of an AND-NOT trigger element.

Наиболее близким по технической 25 сущности к предлагаемому является формирователь импульсов, содержащий два триггера, элемент И-НЕ, инвертор, два диода, резистор-и конденсатор, причем единичный вход первого триг- 30Closest to the technical essence 25 to the proposed one is a pulse shaper containing two triggers, an NAND element, an inverter, two diodes, a resistor and a capacitor, with a single input of the first trigger 30

Гера соединен со входной шиной и входом элемента И-НЕ, другой вход которого соединен с единичным выходом первого триггера и катодом одного из диодов, первый вывод резистора соединен с шиной источника питания, а другой вывод — с анодами диодов, выводом конденсатора и нулевым входом второго триггера, единичный вход которого соединен с выходом элемента И-НЕ и катодом другого диода и через инвертор — с выходной шиной, а нулевой выход соединен с нулевым входом первого триггера, причем другой вывод конденсатора соединен с общей шиной [2J.Hera is connected to the input bus and the input of the AND-NOT element, the other input of which is connected to the single output of the first trigger and the cathode of one of the diodes, the first output of the resistor is connected to the bus of the power source, and the other output to the anodes of the diodes, the output of the capacitor and the zero input of the second a trigger, the single input of which is connected to the output of the NAND element and the cathode of another diode and through the inverter to the output bus, and the zero output is connected to the zero input of the first trigger, and the other capacitor output is connected to the common bus [2J.

Недостатком известного формирователя импульсов является увеличение длительности выходных сигналов до величины, равной периоду следования входных импульсов при длительности входного сигнала логической единицы, равной длительности выходного импульса, и уменьшение длительности выходных сигналов до величины, равной длительности входного сигнала при длительности входного сигнала логической единицы, меньшей номинальной длительности выходного сигнала.A disadvantage of the known pulse shaper is to increase the duration of the output signals to a value equal to the period of the input pulses when the duration of the input signal of the logical unit is equal to the duration of the output pulse, and to reduce the duration of the output signals to a value equal to the duration of the input signal when the duration of the input signal of the logical unit is less than the nominal output signal duration.

Цель изобретения — повышение стабильности длительности выходного импульса .The purpose of the invention is to increase the stability of the duration of the output pulse.

Поставленная цель достигается тем, что в формирователе импульсов, содержащем два триггера, элемент И-НЕ, инвертор, диод, конденсатор и резистор, один вывод которого соединен с шиной источника питания, а другой с анодом диода и с обкладкой конденсатора, вторая обкладка которого подключена к' общей шине, единичный вход первого триггера соединен со входной шиной и входом элемента И-НЕ, другой вход которого подключен к единичному выходу первого Триггера, а выход элемента И-НЕ — к единичному входу второго триггера, единичный выход второго триггера соединен с катодом диода, анод которого подключен ко входу инвертора, выход которого подключен к нулевым входам триггеров..This goal is achieved by the fact that in a pulse shaper containing two triggers, an NAND element, an inverter, a diode, a capacitor and a resistor, one output of which is connected to the power supply bus, and the other to the diode anode and to the capacitor lining, the second lining of which is connected to the common bus, the single input of the first trigger is connected to the input bus and the input of the NAND gate, the other input of which is connected to the single output of the first Trigger, and the output of the NAND gate to the single input of the second trigger, the unit output of the second trigger pa is connected to the cathode of the diode, the anode of which is connected to the input of the inverter, the output of which is connected to the zero inputs of the triggers ..

На чертеже представлена принципиальная схема предлагаемого формирователя импульсов.The drawing shows a schematic diagram of the proposed pulse shaper.

Формирователь импульсов состоит из двух триггеров 1 и 2, элемента ИНЕ 3, инвертора 4, диода 5, резистора б, конденсатора 7, причем единичный вход триггера 1 соединен со входом 8 и входом элемента И-НЕ 3, другой вход:которого подключен к единичному выходу триггера 1, а выход элемента И-НЕ 3 — к единичному входу триггера 2, нулевой выход которого связан с выходом 9 формирователя, а единичный — с катодом диода 5, анод которого соединен со входом инвертора 4,выход которого подключен к нулевым входам триггеров 1 и 2, с одним выводом резистора 6, второй вывод которого соединен с шиной 10 источника питания, и конденсатбром 7, второй вывод которого соединен с общей шиной.The pulse shaper consists of two triggers 1 and 2, an INE 3 element, an inverter 4, a diode 5, a resistor b, a capacitor 7, and the single input of trigger 1 is connected to the input 8 and the input of the AND-NOT 3 element, the other input: which is connected to a single trigger 1, and the output of AND-NOT 3 element to the single input of trigger 2, the zero output of which is connected to the output 9 of the driver, and the single one is connected to the cathode of the diode 5, the anode of which is connected to the input of the inverter 4, the output of which is connected to the zero inputs of the triggers 1 and 2, with one terminal of resistor 6, the second terminal to which is connected to the bus 10 of the power source, and a condensate 7, the second terminal of which is connected to a common bus.

Формирователь работает следующим образом.Shaper works as follows.

В исходном состоянии на вход 8 формирователя поступает уровень логического нуля. Конденсатор 7 раэряжен₇а на выходах триггера 1, элемента ЙНЕ 3,инвертора 4,выходе 9 формирователя — уровни логической единицы.In the initial state, the input of the shaper receives a logic zero level. Capacitor 7 is switched _{on 7} and at the outputs of trigger 1, element JNE 3, inverter 4, output 9 of the shaper - levels of a logical unit.

При поступлении на вход 8 уровня логической единицы на выходе элемента И-НЕ 3 устанавливается уровень логического нуля, триггер 2 переключается и на выходе 9 формируется уровень логического нуля. В дальнейшем процесс формирования выходного сигнала протекает независимо от уровня входного сигнала. Конденсатор 7 начинает заряжаться через резистор 6 от шины 10 источника питания. В момент достижения напряжения на конденсаторе уровня переключения инвертора 4 на выходе последнего появляется нулевой уровень и оба триггера 1 и 2 переключаются, а конденсатор 7 разряжается через диод 5.Upon receipt of input of level 8 of a logical unit at the output of the AND-NOT 3 element, the level of logical zero is set, trigger 2 is switched and output 9 forms the level of logical zero. In the future, the process of generating the output signal proceeds regardless of the level of the input signal. The capacitor 7 begins to be charged through the resistor 6 from the bus 10 of the power source. When the voltage at the capacitor of the switching level of the inverter 4 is reached, the zero level appears at the output of the last one and both triggers 1 and 2 are switched, and the capacitor 7 is discharged through diode 5.

Триггер 1 и элемент И-НЕ 3 служат для поддержания уровня логической единицы на единичном входе триггера 2, обеспечивая разряд конденсатора 7 сразу же после зарада его до порога переключения инвертора 4. Возврат триггера 1 в исходное состояние происходит в момент поступления на вход 8 уровня логического нуля, если длительность входного сигнала логической единицы превышает длительность выходного импульса, в противном случае триггер 1 не изменяет своего состояния за весь цикл работы.Trigger 1 and the AND-NOT 3 element serve to maintain the level of a logical unit at a single input of trigger 2, providing a discharge of capacitor 7 immediately after it has been infected before the threshold of switching of inverter 4. Trigger 1 returns to its initial state when the logic level 8 arrives at input 8 zero if the duration of the input signal of a logical unit exceeds the duration of the output pulse, otherwise trigger 1 does not change its state for the entire cycle of operation.

Подключение выхода инвертора 4 к нулевым входам триггеров 1 и 2 и соединение его входа с анодом диода 5, катод которого подключен к единичному выходу второго триггера 2, позволяет заряжать конденсатор 7 до порога переключения инвертора 4 независимо от длительности входного сигнала логической единицы и тем самым повысить стабильность длительности выходного импульса. Минимальная длительность входных сигналов ограничивается лишь быстродействием микросхем формирователя.Connecting the output of the inverter 4 to the zero inputs of the triggers 1 and 2 and connecting its input to the anode of the diode 5, the cathode of which is connected to the unit output of the second trigger 2, allows you to charge the capacitor 7 to the switching threshold of the inverter 4, regardless of the duration of the input signal of the logical unit and thereby increase stability of the duration of the output pulse. The minimum duration of the input signals is limited only by the speed of the driver chips.

Claims

The invention relates to a pulse technique and can be used in devices of digital technology. A pulse shaper is known, consisting of two AND-NOT elements, an inverter and an integrating RC circuit, with the two IS-NOT elements being connected according to a trigger circuit and the output of one of them: they are connected to the input of the other through an inverter connected in series and an integrating RC circuit . The disadvantage of this former is the instability of the duration of the output pulses at the duration of the logical zero signal at the input of the former, a smaller charge time of the capacitor from the logical zero level to the level of the logical unit, and the complete failure of the former at the input time of the logical zero signal from the input capacitor the level of logic zero to the threshold of switching the element AND IS NOT a trigger. The closest in technical essence to the present invention is a pulse shaper containing two flip-flops, an IS-NE element, an inverter two diodes, a resistor and a capacitor, the single input of the first IFAP triangle connected to the input bus and the input of the IS-NOT element, the other input of which is connected with a single output of the first trigger and the cathode of one of the diodes, the first terminal of the resistor is connected to the power supply bus, and the other output is connected to the anodes of the diodes, the capacitor terminal and the zero input of the second trigger, whose single input is connected to The output of the NAND element and the cathode of another diode and through the inverter is from the output bus, and the zero output is connected to the zero input of the first trigger, with the other capacitor lead connected to the common bus 2j. A disadvantage of the known pulse former is to increase the duration of the output signals to a value equal to the follow-up period of the input pulses when the input signal length is a logical unit equal to the duration of the output pulse, and to reduce the duration of the output signals to a value equal to the duration of the input unit less than nominal duration of the output signal. The purpose of the invention is to increase the stability of the duration of the output pulse. The goal is achieved by the fact that in a pulse shaper containing two triggers, an IS-NOT element, an inverter, a diode, a capacitor and a resistor, one output of which is connected to the power supply bus and the other to the diode anode and the capacitor plate, the second lining of which is connected to the common bus, the single input of the first trigger is connected to the input bus and the input of the NAND element, the other whose input is connected to the single output of the first 1 rigger, and the output of the AND-NC element to the single input of the second trigger, the single output of the second trigger The cable is connected to the cathode of the diode, the anode of which is connected to the input of the inverter, whose output is connected to the zero inputs of the flip-flops. The drawing shows a schematic diagram of the proposed form of the body of pulses. The pulse shaper consists of two triggers 1 and 2, an INE 3 element, an inverter 4, a diode 5, a resistor b, a capacitor 7, and the single input of the trigger 1 is connected to the input 8 and the input of the AND-NOT element 3, the other input: The main output of the trigger 1, and the output of the element AND-NOT 3 - to a single input of the trigger 2, zero output of which is connected to the output 9 of the driver, and a single output with the cathode of the diode 5, the anode of which is connected to the input of the inverter 4, the output of which is connected to zero to the trigger inputs 1 and 2, with one output of resistor b, the second output torogo on bus 10 is coupled to a power source, and a condenser 7, the second terminal of which is connected to the common bus. The shaper works as follows. In the initial state, the log level arrives at the input 8 of the imager. ches zero The capacitor 7 size Zhen and at the outputs of the trigger 1, the element EE 3, inverter 4, 9 output 9 of the driver - the levels of the logical unit. When a logical unit arrives at level 8 input, the logical zero level is set at the output of the NAND element 3, the trigger 2 switches and the level of logical zero is formed at output 9. In the future, the process of forming the output signal proceeds regardless of the input signal level. The capacitor 7 starts charging through the resistor b from the power supply bus 10. When the voltage on the capacitor 7 is reached, the switching level of the inverter 4 at the output of the latter appears to be zero and both flip-flops 1 and 2 switch, and the capacitor 7 discharges through the diode 5. Trigger 1 and the NAND element 3 serve to maintain the logic level units at the unit input of trigger 2, ensuring the discharge of capacitor 7 immediately after charging it before the switching threshold of the inverter 4. The reset of trigger 1 to the initial state occurs at the moment logic level 0 arrives at input 8, if the duration of the input signal and the logical unit exceeds the duration of the output pulse, otherwise trigger 1 does not change its state over the entire cycle of operation. Connecting the output of inverter 4 to the zero inputs of flip-flops 1 and 2 and connecting its input to the anode of diode 5, the cathode of which is connected to the unit output of the second trigger 2, allows the capacitor 7 to be charged up to the switching threshold of the inverter 4, regardless of the input signal most increase the stability of the duration of the output pulse. The minimum duration of the input signals is limited only by the speed of the driver chips. The invention includes a pulse shaper comprising two triggers, an AND-NE element, an inverter, a diode, a capacitor and a resistor, one output of which is connected to the power supply bus and the other to the diode anode and the capacitor plate, the second lining of which is connected to the common bus, the single input of the first trigger is connected to the input bus and the input of the NAND element, the other input of which is connected to the single output of the first trigger, and the output of the NAND element — to the single input of the second trigger, characterized in that the output pulse duration, the single output of the second trigger is connected to the cathode of the diode, the anode of which is connected to the input of the inverter, the output of which is connected to the zero inputs of the trigger. Sources of information taken into account during the examination 1. Instruments and experimental equipment, 1973, No. 4, p.12, fig. 13.

2. Authors certificate of the USSR 621077, cl. H 03 K 5/04, 1977.