SU785976A1 - Pulse shaper by fore and rear fronts of input pulse - Google Patents

Description

The invention relates to a converter technique. A pulse shaper is known that allows to obtain an output pulse along the leading and trailing edges of the input pulse ij. However, the output pulses of a known device are formed directly on the edges of the input pulse and, therefore, for further use in clocked systems, their additional synchronization is necessary. Also known is a pulse former on the leading and trailing edges of the input pulse, including a time stamp generator, three triggers, a counter, two NAND elements, a matching element, and a pulse duration control unit. The disadvantages of this pulse former are the impossibility of obtaining a pulse along the trailing edge of the input pulse in the case of an input pulse shorter than the counter filling time, and the accuracy of the output pulses due to the fact that the leading edge of the output pulse starts directly on the front of the input pulse and, consequently, the duration may vary within the pause duration of the time stamp pulses. The aim of the invention is to improve the accuracy of the formed output pulses and expansion functionality shaper. The goal is achieved in that the pulse shaper is on the leading and trailing edges of the input pulse, containing three flip-flops, a counter, two NAND units, a matching element, a pulse duration control unit and a time stamp generator, the R-inputs of the first and second triggers are connected with the output of the pulse duration control unit, the inputs of which are connected to the counter outputs, and the inverse output of the first trigger is connected to the first inputs of the coincidence element and. of the first element AND-NOT, an additional element IS-NOT is introduced, the inputs of which are connected to the inverted outputs of the counter, the addition input of which is connected to the output of the second AND-NOT element and the C input of the second trigger, the D INPUT of which is connected to first trigger and first

the input of the second NAND element, BTOpoJt, whose input is connected to the R input of the first trigger, the S input of which is connected to the second input of the first NAND element, the output of which is connected to the counter subtraction input and the C input of the third trigger, 1) input which is connected to the first input of the coincidence element, the second input of which is connected to the output of the additional AND-NOT element, ft-input of the third trigger and the third input of the first AND-NOT element, the fourth input of which is connected to the third input of the second AND-NOT element and the output of the temporary generator tags.

The drawing shows the block diagram of the device.-,

The pulse shaper on the leading and trailing edges of the input pulse contains triggers 1–3, counter 4, AND – NE elements 5–7, match element 8, pulse duration control unit 9, and time stamp generator 10.

The shaper works as follows.

In the initial state, the triggers 1-3 and the counter 4 are in the zero state. In this case, at the output of the element AND-NOT 7 there will be a low potential, which closes the element AND-NOT 6 at the third input, and the element AND-NE 5 is closed at the first input with a low potential of the unit output of the trigger 1.

When the input pulse of negative polarity arrives, trigger 1 is set to one state, opening the first input element AND-NOT 5 and closing the first input element AND-NOT 6 and element 8. At the J) input of the trigger 2, a high potential single output of trigger 1, and inverted impulses of generator 10 are formed at the output of element I-HE 5. The first difference from low to high level from output of element I-HE 5 (the falling front of the generator of time stamps) arrives at C-input of trigger 2 and to the addition of the counter 4, triggers trigger 2 to one state and writes one to counter. In this case, the output edge of the output pulse is formed at the output of the trigger 2 along the leading edge of the input signal, and at the output of the NAND 7 element there appears a high Lotencyssh which opens the IS-NE 6 and the element 8 through the second inputs.

When the counter reaches 4, the state to which block 9 is installed, a low potential appears at the output of the latter, which closes the AND-HE element 5 at the second input, thereby stopping the input from the generator 10 to the addition input

counter 4, returns to the initial state trigger 2, forms the trailing edge of the favorable pulse on the leading edge of the input signal, and sets a high potential at the zero output of the trigger 1, the opening element AND-NOT b and the element 8 at the first input and the actions at 3) - trigger input 3.

If the input pulse has already ended by that time, then trigger 1 is set to the zero state, closing the first input element AND-NOT 5, and the AND-NOT element 6 will also be opened at the second input by high potential from the input sigigs bus and closed the fourth input has a low pause potential of the time stamp generator, i.e. at the output of the element AND-HE 6, the high potential is preserved, and then inverted pulses of the generator 10 are formed. The first difference from low to high level from the output of the element AND-HE 6, arriving at the C input of the trigger 3 and to the subtraction input of the counter 4, translates trigger 3 into one state (AND writes 4 units into counter 4. In this case, the output edge of the trigger 3 forms the leading edge of the output pulse along the trailing edge of the input signal, and the output of block 9 shows a high potential, which opens the AND-NOT 5 by to the second entrance. By the zero-state counter 4, a low potential appears at the output of the NAND 7 element, which closes the element 8 and the third input on the second input of the NAND element, thereby stopping the flow of the generator 10 pulses to the subtraction input of the counter 4, and returns trigger 3 to the initial state, forming the trailing edge of the output pulse on the trailing edge of the input signal.

Thus, the pulse shaper produces pulses along the leading and trailing edges of the input signal, the duration of which is equal to several periods of the IM pulse pulses of the time meters, the number of which is determined by the pulse duration control unit and is limited by the counter capacity. In this case, at the output of the element IS-NE 7, pulses are formed with a hollow trailing edge relative to the input pulse, at the output of block 9 pulses are formed with a delayed leading edge relative to the input pulse, and at the output of element 8 pulses with delayed leading and trailing edges i.e. delayed input pulse. -The magnitude of the delay is equal to the duration of the output pulses at the front and rear frontil of the input pulse.

Claims (2)

1. The copyright certificate of GCCP 0 455468, cl. And 03 K 5/04, 1975. 2. Author's certificate of the USSR 611297, cl. H 03 K 5/04, 1976 . (prototype).