SU782142A1 - Pulse-phase detector - Google Patents

Description

- The invention relates to radio engineering and can be used in information-measuring equipment and pulse-phase locked loop systems.

Known pulse-phase detector containing parallel connected integrating capacitor and discharge key.

The disadvantage of this device is the impulse noise at the comparison frequency.

A pulse-phase detector is known, which contains an integrating capacitor, a key of a scanner unit, a 5- memory unit, a key and a first trigger, a memory unit key £ 2j.

The disadvantage of this device is its low noise immunity.

The purpose of the invention is to increase mechanical protection.

This goal is achieved by the fact that in the pulse-phase detector containing an integrating capacitor, a transistor of a scan unit, a storage unit 25, a transistor, a first trigger, a key of a storage unit, a phase difference unit, an OR-HE unit, a second trigger, three delay units are introduced, two . buffer blocks, resistors, with 30 first and second inputs of the phase difference unit • connected respectively to the first and second input bus, and the first and second output of the phase difference unit connected to the first and second input of the first trigger, the first output of which is connected to the control input of the transistor scanner, and the second output is with the first input of the OR-HE block, the second input of which is connected to the first input of the first trigger, the output of the block. OR NOT connected to the first input of the second trigger, the output of which is connected through the first delay unit to the input of the second delay unit and to the first input of the key of the storage unit, the second input of the key of the storage unit is connected to the output of the second delay unit and the input of the third delay unit, the output of which is connected with the second input of the second trigger and with the base of the transistor, the collector of which is connected to the common bus, and the emitter through the first · resistor to the common output of the collector of the transistor of the scanner unit and the first lining of the integrating condenser sator, the second lining of which is connected to the common bus, the emitter of the transistor of the scanner unit is connected through the second resistor to the supply bus, the output of the integrating capacitor is connected through the first buffer block / key of the memory block, the memory block, the second buffer block with the output of the detector.

In FIG. 1 shows a structural * electric circuit of a pulse-phase detector ·, FIG. G * 2 is a voltage diagram.

The pulse-phase detector contains an integrating capacitor 1, trans-eistor 2, a scan unit, a memory unit 3, a transistor 4, a first trigger 5, a memory unit key 6, a phase difference unit 7, an OR-HE block 8, a second trigger 9, three block 10-12 delay-15 ki, two buffer blocks 13 and 14, resistors 15 and 16.

Pulse-phase detector operates as follows.

The initial state is taken at the 20th time moment, when the log levels O. are present on the first outputs of the block 7 of the phase difference and triggers 5 and 9, and the log levels are on the second outputs. 1 (Fig. 2) and transistors 2 and 4 are closed, at the output of block 8 - * · * level log. 0 (Fig. 2).

The input signals are fed to the phase difference unit 7, from the output of which a vapor-phase signal with a duration of jq is proportional to the phase difference is fed to the inputs of the first trigger 5. When ^! changing the signal at the first input of trigger 5 from the log level. 0 (Fig.2) • to the level log. 1 (FIG. 2), and at the second 35th input - from the log level. 1 (figure 2) to the level of the log. 0 (Fig. 24, the first trigger 5 will switch to the state when its first output will be log level 1 (Fig. 2), and the second - log level 0 (Fig. 2), while the transistor 2 of the scan unit will open and the charge of the integrating capacitor 1 will begin. At the output of block 8, the log level 0 will be saved. (Fig. 2). At the end of the signal, the levels at the inputs 45 of the first trigger 5 take the initial state (the first input is log level 0, the second is log level 1 ). Since there is still jq at the second output of the first trigger 5 at this moment in time. There is a log level of 0, then it appeared at the second input Lock 8 level logic 0 will lead to a change in its output of level logic 0 to level 1, which will trigger the second trigger 9. Somewhat earlier, the first trigger 5 will return to its original state and close transistor 2, stopping the charge of the integrating capacitor 1. Thus, the charge time of the integrating ^: capacitor 60 corresponds to the duration of the incoming pulse from the phase difference unit 7. After the end of the charge of the integrating capacitor 1, the storage time of its charge begins. . > 5 • Switching the second trigger 9 causes the appearance of the log level at its output. 1, which, through the first delay block 10, enters the first input of the key 6 of the memory unit and opens it, overwriting it from the integrating codenser 1, which performs the function of intermediate storage, through the input buffer block 13 to the memory block 3 and through the output buffer block 14 to the output devices. After a time equal to the delay of the second block 11 delay level log. 1 enters the second control input of the storage key and closes it. After a time equal to the delay of the third delay block 12, the level of log.1 will go to the base of transistor 4 and open it. A relatively slow discharge of the integrating capacitor 1 begins through the current-limiting resistor 15. The storage time of the charge on the integrating capacitor ends. Simultaneously with the output of the third block 12 delay signal level log. 1 enters the second input of the second trigger 9 and returns it to its original state. After a time equal to the sum of the delays of the delay blocks 1012, the signal from the output of the second trigger 9 with the log level. 0 closes transistor 4. Then, the operation cycle will be repeated.

Thus, an asymmetrical-trapezoidal form of the unfolding voltage, shown in FIG. 2) where it is shown that during the period of period 17 there is a sweep 18, storage 19, discharge 20, a pause 21 between the end of the discharge and the beginning of the sweep, while the storage time 19 is determined by the total delay of three blocks 10-12.

The delay time 22 of the first delay unit 10 should be longer than the transient time in the scan unit when switching from the scan mode to the storage mode. The delay time 23 of the second delay unit 11 is determined by the time% of recording, which should be more than the transient time in the key 6 of the memory unit 3. The delay time 24 of the delay unit 12 should be longer than the transient process of locking the key.

Using the asymmetric-trapezoidal form of the deployment voltage allows you to significantly reduce the amplitude of the voltage surge and the time it takes to establish transients of the deployment device, especially when changing the sweep mode to discharge.

Claims (2)

1. USSR author's certificate 0 471654, cl. Oz 13/00, 1973. 2. Authors certificate of the USSR 484636, cl. H 03 K 9/04, 1973.